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document no. e1797e41 (ver. 4.1) date published february 2012 (k) japan printed in japan url: http://www.elpida.com ? elpida memory, inc. 2011-2012 data sheet 2g bits ddr3l sdram EDJ2104EDBG (512m words 4 bits) edj2108edbg (256m words 8 bits) specifications ? density: 2g bits ? organization ? 64m words 4 bits 8 banks (EDJ2104EDBG) ? 32m words 8 bits 8 banks (edj2108edbg) ? package ? 78-ball fbga ? lead-free (rohs compliant) and halogen-free ? power supply: 1.35v (typ.) ? vdd, vddq = 1.283v to 1.45v ? backward compatible for vdd, vddq = 1.5v 0.075v ? data rate ? 1600mbps/1333mbps/1066mbps (max.) ? 1kb page size ? row address: a0 to a14 ? column address: a0 to a9, a11 (EDJ2104EDBG) a0 to a9 (edj2108edbg) ? eight internal banks for concurrent operation ? burst lengths (bl): 8 and 4 with burst chop (bc) ? burst type (bt): ? sequential (8, 4 with bc) ? interleave (8, 4 with bc) ? /cas latency (cl): 5, 6, 7, 8, 9, 10, 11 ? /cas write latency (cwl): 5, 6, 7, 8 ? precharge: auto precharge option for each burst access ? driver strength: rzq/7, rzq/6 (rzq = 240 ? ) ? refresh: auto-refresh, self-refresh ? refresh cycles ? average refresh period 7.8 s at 0 c tc + 85 c 3.9 s at + 85 c < tc + 95 c ? operating case temperature range ? tc = 0 c to +95 c features ? double-data-rate architecture: two data transfers per clock cycle ? the high-speed data transfer is realized by the 8 bits prefetch pipelined architecture ? bi-directional differential data strobe (dqs and /dqs) is transmitted/received with data for capturing data at the receiver ? dqs is edge-aligned with data for reads; center- aligned with data for writes ? differential clock inputs (ck and /ck) ? dll aligns dq and dqs transitions with ck transitions ? commands entered on each positive ck edge; data and data mask referenced to both edges of dqs ? data mask (dm) for write data ? posted /cas by programmable additive latency for better command and data bus efficiency ? on-die termination (odt) for better signal quality ? synchronous odt ? dynamic odt ? asynchronous odt ? multi purpose register (mpr) for pre-defined pattern read out ? zq calibration for dq drive and odt ? programmable partial array self-refresh (pasr) ? /reset pin for power-up sequence and reset function ? srt range: ? normal/extended ? programmable output driver impedance control
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 2 ordering information part number die revision organization (words bits) internal banks jedec speed bin (cl-trcd-trp) package EDJ2104EDBG-gn-f EDJ2104EDBG-dj-f EDJ2104EDBG-ae-f d 512m 4 8 ddr3l-1600k (11-11-11) ddr3l-1333h (9-9-9) ddr3l-1066f (7-7-7) 78-ball fbga edj2108edbg-gn-f edj2108edbg-dj-f edj2108edbg-ae-f 256m 8 ddr3l-1600k (11-11-11) ddr3l-1333h (9-9-9) ddr3l-1066f (7-7-7) note: 1. please refer to the edj2104bdbg, edj2108bdbg datasheet (e1772e) when using this device at 1.5v operation, unless stated otherwise. part number elpida memory density / bank 21: 2gb / 8-bank organization 04: x4 08: x8 power supply e: 1.35v die rev. package bg: fbga speed gn: ddr3l-1600k (11-11-11) dj: ddr3l-1333h (9-9-9) ae: ddr3l-1066f (7-7-7) product family j: ddr3 type d: packaged device e d j 21 04 e d bg - gn- f environment code f: lead free (rohs compliant) and halogen free
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 3 pin configurations /xxx indicates active low signal. vss vdd 1 vddq vss vss 2 vssq dq0 vss dq2 nc vssq vddq vrefdq vss vdd /cs ba0 a7 /reset nc nc vdd 3 nc dqs /dqs nc /ras /cas /we ba2 a9 a13 7 nc dm dq1 vdd nc ck /ck a10(ap) nc a11 a14 8 vss vssq vddq vssq dq3 vss nc vss vdd zq vrefca a6 a8 cke vss vss 9 vdd vssq vddq nc vdd (top view) 78-ball fbga ( 4 configuration) odt nc a b c d e f g h j a3 vdd a0 a12(/bc) ba1 vdd a5 vss a2 a1 a4 vss k l m n vss vdd 1 vddq vss vss 2 vssq dq0 vss dq2 dq6 vssq vddq vrefdq vss vdd /cs ba0 a7 /reset nc nc vdd 3 nc dqs /dqs dq4 /ras /cas /we ba2 a9 a13 7 nu/(/tdqs) dm/tdqs dq1 vdd dq7 ck /ck a10(ap) nc a11 a14 8 vss vssq vddq vssq dq3 vss dq5 vss vdd zq vrefca a6 a8 cke vss vss 9 vdd vssq vddq nc vdd (top view) 78-ball fbga ( 8 configuration) odt nc a b c d e f g h j a3 vdd a0 a12(/bc) ba1 vdd a5 vss a2 a1 a4 vss k l m n pin name function pin name function a0 to a14* 3 address inputs a10 (ap): auto precharge a12(/bc): burst chop /reset* 3 active low asynchronous reset ba0 to ba2* 3 bank select vdd supply voltage for internal circuit dq0 to dq7 data input/output vss ground for internal circuit dqs, /dqs differential data strobe vddq supply voltage for dq circuit tdqs, /tdqs termination data strobe vssq ground for dq circuit /cs* 3 chip select vrefdq reference voltage for dq /ras, /cas, /we* 3 command input vrefca reference voltage cke* 3 clock enable zq reference pin for zq calibration ck, /ck differential clock input nc* 1 no connection dm write data mask nu* 2 not usable odt* 3 odt control notes: 1. not internally connected with die. 2. don?t connect. internally connected. 3. input only pins (address, command, c ke, odt and /reset) do not supply termination.
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 4 contents specifications................................................................................................................. ................................1 features....................................................................................................................... ..................................1 ordering in format ion........................................................................................................... ...........................2 part nu mber .................................................................................................................... ..............................2 pin config urations ............................................................................................................. ............................3 electrical conditions .......................................................................................................... ............................6 absolute maxi mum ra tings ....................................................................................................... ..................6 operating temperat ure cond ition ................................................................................................ ...............6 recommended dc operating conditions (tc = 0 + = recommended dc operating conditions (tc = 0 + = ac and dc input measurement levels (tc = 0 + = vref tole rances ................................................................................................................ ........................9 input slew ra te dera ting ....................................................................................................... .................... 10 ac and dc logic input levels for differentia l sign als .......................................................................... ..... 16 ac and dc output measurement levels (tc = 0 + = ac overshoot/undershoo t specific ation.......................................................................................... .......... 23 output driver imped ance........................................................................................................ ................... 24 on-die termination (odt) level s and i-v char acterist ics ........................................................................ 26 odt timing de finiti ons......................................................................................................... ..................... 28 idd measurement conditions (tc = 0 + = electrical sp ecifications...................................................................................................... .........................45 dc characteristics 1 (tc = 0 + = pin capacitance (tc = 25 = standard speed bins ............................................................................................................ ..................... 48 ac characteristics (tc = 0 + = = block diagram .................................................................................................................. ...........................64 pin function................................................................................................................... ..............................65 command oper ation .............................................................................................................. .....................67 command trut h tabl e ............................................................................................................ ................... 67 cke truth table ................................................................................................................ ........................ 71 simplified stat e diag ram ....................................................................................................... ......................72 reset and initializat ion procedure ............................................................................................. ...............73 power-up and initia lization se quence ........................................................................................... ............ 73 reset and initializati on with stabl e power ..................................................................................... ............ 74 programming the mode register.................................................................................................. ...............75 mode register set command cycle time (tmrd) .................................................................................... 75 mrs command to non-mrs command dela y (tmo d) ............................................................................ 75 ddr3 sdram mode regi ster 0 [mr0] ............................................................................................... ...... 76 ddr3 sdram mode regi ster 1 [mr1] ............................................................................................... ...... 77
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 5 ddr3 sdram mode regi ster 2 [mr2] ............................................................................................... ...... 78 ddr3 sdram mode regi ster 3 [mr3] ............................................................................................... ...... 79 burst length (mr0) ............................................................................................................. ...................... 80 burst type (mr0) ............................................................................................................... ....................... 80 dll enabl e (mr 1) ............................................................................................................... ...................... 81 dll-off mode ................................................................................................................... .......................... 81 dll on/off switch ing proc edure ................................................................................................. ................ 82 additive lat ency (mr1)......................................................................................................... ..................... 84 write level ing (mr 1) ........................................................................................................... ...................... 85 tdqs, /tdqs f unction (mr1) ..................................................................................................... .............. 88 extended temperat ure usag e (mr 2) ............................................................................................... ......... 89 multi purpose r egister (mr3)................................................................................................... ................. 91 operation of t he ddr3 sdram .................................................................................................... ..............98 read timing de finition......................................................................................................... ...................... 98 read oper ation ................................................................................................................. ...................... 103 write timing defini tion........................................................................................................ ..................... 110 write oper ation................................................................................................................ ........................ 112 write timing violat ions ........................................................................................................ .................... 118 write data mask ................................................................................................................ ...................... 119 prechar ge ...................................................................................................................... .......................... 120 auto precharge operat ion ....................................................................................................... ................ 121 auto-ref resh................................................................................................................... ......................... 122 self-ref resh................................................................................................................... .......................... 123 power-dow n m ode ................................................................................................................ .................. 125 input clock frequency change dur ing precharge power-down.............................................................. 132 on-die terminat ion (o dt)....................................................................................................... ................ 133 zq calib ration................................................................................................................. ......................... 145 package drawing ................................................................................................................ ......................147 78-ball fbga ................................................................................................................... ........................ 147 recommended solder ing conditions............................................................................................... .........148
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 6 electrical conditions ? ? ? + ? + ? + ? + ? ? ? + : + : + + + : = =
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 7 recommended dc operating conditions (tc = 0 + = : = + = : t (min.) = 10ns t (min.) = 200 s t (min.) = 10ns t = 500 s tis note: 1. from time point td until tk nop or desl commands must be applied between mrs and zqcl commands. : vih or vil ck, /ck vdd, vddq (ddr3) vdd, vddq (ddr3l) /reset cke command ba odt rtt txpr tmrd tmrd tmrd tmod tcksrx tis tis ta tb tc td te tf tg th ti tj tk t (min.) = 10ns tdllk tzqinit *1 *1 valid valid valid valid mrs static low in case rtt_nore is enabled at time tg, otherwise static high or low mrs mrs mrs zqcl mr2 mr3 mr1 mr0
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 8 ac and dc input measurement levels (tc = 0 + = + ? ? ? + ? ? ? ? ? + ? ? ? ? ? ? : = : : + ? ? ? ? ? ? + ? ? + ? ? ? ? ? ? ? ? ? ? ? ? : : = : :
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 9 vref tolerances the dc-tolerance limits and ac-noise limits for the reference voltages vr efca and vrefdq are shown in figure vref(dc) tolerance and vref ac-noise limits. it shows a valid reference voltage vref(t) as a function of time. (vref stands for vrefca and vrefdq likewise). vref(dc) is the linear average of vref(t) over a very long period of time (e.g. 1 sec). this average has to meet the min/max requirements in the tabl e of(single-ended ac and dc input levels for command and address). furthermore vref(t) may temporarily deviate fr om vref(dc) by no more than +/- 1% vdd.

vref(dc) tolerance and vref ac-noise limits the voltage levels for setup and hold time measurement s vih(ac), vih(dc), vil(ac ) and vil(dc) are dependent on vref. vref shall be understood as vref(dc), as defined in fi gure above, vref(dc) tolerance and vref ac-noise limits. this clarifies that dc-variations of vref affect the absolute voltage a signal has to reach to achieve a valid high or low level and therefore the time to which setup and hold is measured. system timing and voltage budgets need to account for vref(dc) deviations from the optimum pos ition within the data-eye of the input signals. this also clarifies that the dram setup/hold specification and derating values need to include time and voltage associated with vref ac-noise. timing and voltage effect s due to ac-noise on vref up to the specified limit (
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 10 input slew rate derating for all input signals the total tis, tds (setup time) and tih, t dh (hold time) required is calculated by adding the data sheet tis (base), tds (base) and tih (base), tdh (base) value to the ? ? ? ? : = + ? : ?
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 11 [derating values of tis/tih ac/dc based ac160 threshold (ddr3l-1600, 1333, 1066)] ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ? ? ? ? ? ? + + + + + + + + + + ? ? ? ? ? ? + + + + + + + + + + ? ? ? ? ? ? + ? + + + + + + + + ? ? ? ? ? ? ? + ? + + + + + + ? ? ? ? ? ? ? ? ? ? + ? + + + + ? ? ? ? ? ? ? ? ? ? ? ? ? ? + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ? + ? + ? + + + + + + + + + + + ? + ? + ? + + + + + + + + + + + ? + ? + ? + ? + + + + + + + + + ? + ? + ? + ? + ? + + + + + + + ? + ? + ? + ? + ? + ? + + + + ? ? ? ? ? ? + ? + ? + ? + ? + + > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? < ? ?
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 12 [data setup and hold base-values] ddr3l-1600 ddr3l-1333 ddr3l-1066 unit reference tds(base) ac160 ? ? : ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + + + + + + ? ? ? ? ? ? ? ? ? ? + + + + + + + + ? ? ? ? ? ? ? ? + + + + ? ? ? ? ? ? ? ? ? ? ? ? + + + + + + ? ? ? ? ? ? ? ? ? ? + + + + + + + + ? ? ? ? ? ? ? ? + ? + + + + + + + + ? ? ? ? ? ? ? ? + ? + + + + + + ? ? ? ? ? ? ? ? ? ? + ? + + + + ? ? ? ? ? ? ? ? ? ? ? ? ? ? + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + + + + + + ? ? ? ? ? ? ? ? ? ? + + + + + + + + ? ? ? ? ? ? ? ? + + + + ? ? ? ? ? ? ? ? + ? + ? + + + + + + ? ? ? ? ? ? ? ? + ? + + + + + + + + ? ? ? ? ? ? ? ? + ? + + + + + + + + ? ? ? ? ? ? ? ? + ? + + + + + + ? ? ? ? ? ? ? ? ? ? + ? + + + + ? ? ? ? ? ? ? ? ? ? ? ? + ? + +
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 13 [required time tvac above vih(ac) {b elow vil(ac)} for valid transition] ddr3l-1066 (ac160) ddr3l-1600, 1333, 1066 (ac135) tvac [ps] tvac [ps] slew rate (v/ns) min. max. min. max. > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? < ? ?
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 14 vdd tis tih tis tih vref to ac region vref to ac region dc to vref region dc to vref region nominal slew rate nominal slew rate ? tfs ? trh ? tfh ? trs vss vih (ac) min. vih (dc) min. vil (dc) max. vil (ac) max. vref (dc) tvac tvac ck /ck slew rate definition nominal (ck, /ck) vdd tds tdh tds tdh /dqs dqs vref to ac region vref to ac region dc to vref region dc to vref region nominal slew rate nominal slew rate ? tfs ? trh ? tfh ? trs vss vih (ac) min. vih (dc) min. vil (dc) max. vil (ac) max. vref (dc) tvac tvac slew rate definition nominal (dqs, /dqs) vref (dc) - vil (ac) max. ? tfs setup slew rate falling signal vref (dc) - vil (dc) max. ? trh hold slew rate rising signal = = vih (ac) min. - vref (dc) ? trs setup slew rate rising signal vih (dc) min. - vref (dc) ? tfh hold slew rate falling signal = =
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 15 vdd tis tih tis tih vref (dc) vih (ac) min. vih (dc) min. vil (dc) max. vil (ac) max. vss vref to ac region vref to ac region dc to vref region dc to vref region nominal line nominal line nominal line nominal line tangent line tangent line ? tfs ? trh ? tfh ? trs tvac tvac ck /ck slew rate definition tangent (ck, /ck) vdd tds tdh tds tdh vref (dc) vih (ac) min. vih (dc) min. vil (dc) max. vil (ac) max. vss vref to ac region vref to ac region dc to vref region dc to vref region nominal line nominal line nominal line nominal line tangent line tangent line ? tfs ? trh ? tfh ? trs /dqs dqs tvac tvac slew rate definition tangent (dqs, /dqs) tangent line [vref (dc) - vil (ac) max.] ? tfs setup slew rate falling signal tangent line [vref (dc) - vil (dc) max.] ? trh hold slew rate rising signal = = tangent line [vih (ac) min. - vref (dc)] ? trs setup slew rate rising signal tangent line [vih (dc) min. - vref (dc)] ? tfh hold slew rate falling signal = =
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 16 ac and dc logic input levels for differential signals differential signal definition

! "#" definition of differential ac-swing and ?time above ac-level? tdvac [differential ac and dc input levels] parameter symbol min. typ. max. unit notes differential input logic high vihdiff + ? ? ? ? ? ? ? ? ? ? :
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 17 [required time tdvac above vih(ac) {b elow vil(ac)} for valid transition] @[vih/ldiff (ac)] = 320mv @[vih/ldiff (ac)] = 270mv tdvac [ps] tdvac [ps] slew rate (v/ns) min. max. min. max. > ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? < ? ?
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 18 single-ended requirements for differential signals each individual component of a differential signal (ck, dqs, /ck, /dqs) has also to comply with certain requirements for single-ended signals. ck and /ck have to reach vseh min. / vsel max. (approx imately equal to the ac-levels (vih(ac) / vil(ac)) for address/command signals) in every half-cycle. dqs, /dqs have to reach vseh min./vsel max. (approximately equal to the ac-levels (vih(ac) / vil(ac)) for dq signals) in every half-cycle preceding and following a valid transition. note that the applicable ac-levels for address/command and dq?s might be differ ent per speed-bin etc. e.g. if vih 135 (ac)/vil 135 (ac) is used for address/command signals , then these ac-levels apply also for the single ended components of differential ck and /ck.
single-ended requirement for differential signals. note that while address/command and dq signal requir ements are with respect to vref, the single-ended components of differential signals have a requirement with respect to vdd / 2; this is nominally the same. the transition of single-ended signals through the ac-levels is used to measure setup time. for single-ended components of differential signals the requirement to reach vsel max, vseh min has no bearing on timing, but adds a restriction on the common mode characteri stics of these signals.
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 19 [single-ended levels for ck, dqs, /ck, /dqs] parameter symbol min. typ. max. unit notes single-ended high level for strobes (vdd/2) + ? ? + ? ? ? ? ? ? ? ? : vix vix vix ck, dqs vdd vdd/2 /ck, /dqs vss vseh vse l vix definition [cross point voltage for differential input signals (ck, dqs)] parameter symbol pins min. max. unit note differential input cross point voltage relative to vdd/2 vix ck, /ck ? ? : + ? ? +
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 20 [differential input sl ew rate definition] measured description from to defined by applicable for note differential input slew rate for rising edge (ck - /ck and dqs - /dqs) vildiff (max.) vihdiff (min.) vihdiff (min.) ? vildiff (max.) ? ? : ? trdiff ? tfdiff vihdiff (min.) ? vildiff (max.) ? tfdiff falling slew = vihdiff(min.) vildiff (max.) 0 vihdiff (min.) ? vildiff (max.) ? trdiff rising slew = differential input slew rate definition for dqs, /dqs and ck, /ck
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 21 ac and dc output measurement levels (tc = 0 + = + ? ? : ? ? = ? ? = ? ? ? trse ? tfse voh (ac) ? vol (ac) ? tfse falling slew = voh (ac) vol (ac) vtt voh (ac) ? vol (ac) ? trse rising slew = output slew rate definition for single-ended signals
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 22 [differential output sl ew rate definition] measured description from to defined by differential output slew rate for rising edge voldiff (ac) vohdiff (ac) vohdiff(ac) ? voldiff (ac ) ? ? ? trdiff ? tfdiff vohdiff (ac) ? voldiff (ac) ? tfdiff falling slew = vohdiff (ac) voldiff (ac) 0 vohdiff (ac) ? voldiff (ac) ? trdiff rising slew = differential output slew rate defi nition for dqs, /dqs and ck, /ck output slew rate (r on = rzq/7 setting) parameter symbol speed min. max. unit notes output slew rate (single-ended) srqse ddr3l-1600 ddr3l-1333 ddr3l-1066 1.75 5 v/ns 1 output slew rate (differential) srqdiff ddr3l-1600 ddr3l-1333 ddr3l-1066 3.5 12 v/ns remark: sr = slew rate. se = single-ended signals . diff = differential signals. q = query output note: 1. in two cases, a maximum slew rate of 6v /ns applies for a single dq signal within a byte lane. (a) is defined for a single dq signal within a byte lane which is switching into a certain direction (either from high to low or low to high) while all remaining dq signals in the same byte lane are static (i.e. they stay at either high or low). (b) is defined for a single dq signal within a byte lane which is switching into a certain direction (either from high to low or low to high) while all remaining dq si gnals in the same byte lane are switching into the opposite direction (i.e. from low to high or high to low respectively). for the remaining dq signal switching into the opposite direction, t he regular maximum limit of 5v/ns applies. reference load for ac timing and output slew rate 25 ? vddq ck, /ck vtt = vddq/2 dut dq dqs, /dqs reference output load
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 23 ac overshoot/undershoot specification parameter pins specification maximum peak amplitude allowed for overshoot command, address, cke, odt tbd maximum peak amplitude allowed for undershoot tbd maximum overshoot area above vdd ddr3l-1600 tbd ddr3l-1333 tbd ddr3l-1066 tbd maximum undershoot area below vss ddr3l-1600 tbd ddr3l-1333 tbd ddr3l-1066 tbd maximum peak amplitude allowed for overshoot ck, /ck tbd maximum peak amplitude allowed for undershoot tbd maximum overshoot area above vdd ddr3l-1600 tbd ddr3l-1333 tbd ddr3l-1066 tbd maximum undershoot area below vss ddr3l-1600 tbd ddr3l-1333 tbd ddr3l-1066 tbd maximum peak amplitude allowed for overshoot dq, dqs, /dqs, dm tbd maximum peak amplitude allowed for undershoot tbd maximum overshoot area above vddq ddr3l-1600 tbd ddr3l-1333 tbd ddr3l-1066 tbd maximum undershoot area below vssq ddr3l-1600 tbd ddr3l-1333 tbd ddr3l-1066 tbd maximum amplitude overshoot area undershoot area volts (v) time (ns) vdd, vddq vss, vssq overshoot/undershoot definition
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 24 output driver impedance ron will be achieved by the ddr3 sdram after proper i/o calibration. tolerance and linearity requirements are referred to the output driver dc el ectrical characteristics table. a functional representation of the output buffer is shown in the figure output driver: definition of voltages and currents. ron is defined by the value of the exte rnal reference resistor rzq as follows: ? = ? = : ? ? ? ? ? vddq vssq v out i out i pu ron pu chip in drive mode to other circuitry like rcv, ... output driver dq i pd ron pd output driver: definition of voltages and currents
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 25 output driver dc electrical characteristics (rzq = 240 ? ? = = = = = = ? = = = = = = = ? + : = = : : = ? = ? ? = ? = : ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 26 on-die termination (odt) levels and i-v characteristics on-die termination effective resistance rtt is defin ed by bits a9, a6 and a2 of the mr1 register. odt is applied to the dq, dm, dqs, /dqs and tdqs, /tdqs ( : : ? ? ? ? ? vddq vssq v out i out i pu rtt pu chip in termination mode to other circuitry like rcv, ... odt dq i out = i pd - i pu i pd rtt pd on-die termination: definition of voltages and currents the value of the termination resistor can be set via mr s command to rtt60 = rzq/4 (nom) or rtt120 = rzq/2 (nom). rtt60 or rtt120 will be achieved by the ddr3 sd ram after proper i/o calibration has been performed. tolerances requirements are referred to t he odt dc electrical characteristics table. measurement definition for rtt apply vih (ac) to pin under test and measure current i(vi h(ac)), then apply vil(ac) to pin under test and measure current i(vil(ac)) respectively. )) ac ( vil ( i )) ac ( vih ( i ) ac ( vil ) ac ( vih rtt ? ? = ? ? ? ? ? ? ? ? ? = ?
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 27 odt dc electrical characteristics (rzq = 240 ? ? ? ? ? ? ? ? : = = : ? ? =
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 28 6. measurement definition for vm and ? : : ? ? ? ? ? ? ? ? = ? ? = ? ? = ? = : ? ? ? ? ? rtt = 25 : vddq ck, /ck vtt = vssq dut dq dqs, /dqs odt timing reference load
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 29 odt measurement definitions definitions for taon, taonpd, taof, taofpd and tadc are provided in the following table and subsequent figures. symbol begin point definiti on end point definition figure taon rising edge of ck - /ck defined by the end point of odtlon extrapolated point at vssq figure a) taonpd rising edge of ck - /ck with odt being first registered high extrapolated point at vssq figure b) taof rising edge of ck - /ck defined by the end point of odtloff end point: extrapolated point at vrtt_nom figure c) taofpd rising edge of ck - /ck with odt being first registered low end point: extrapolated point at vrtt_nom figure d) tadc rising edge of ck - /ck defined by the end point of odtlcnw, odtlcwn4 or odtlcwn8 end point: extrapolated point at vrtt_wr and vrtt_nom respectively figure e) reference settings for odt timing measurements measurement reference settings are pr ovided in the following table. measured parameter rtt_nom setting rtt_wr setting vsw1 [v] vsw2 [v] note taon rzq/4 n/a 0.05 0.10 rzq/12 n/a 0.10 0.20 taonpd rzq/4 n/a 0.05 0.10 rzq/12 n/a 0.10 0.20 taof rzq/4 n/a 0.05 0.10 rzq/12 n/a 0.10 0.20 taofpd rzq/4 n/a 0.05 0.10 rzq/12 n/a 0.10 0.20 tadc rzq/12 rzq/2 0.20 0.25 ck begin point: rising edge of ck - /ck defined by the end point of odtlon end point: extrapolated point at vssq taon tsw2 vsw2 vsw1 tsw1 /ck vssq dq, dm dqs, /dqs tdqs, /tdqs vtt vssq a) definition of taon
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 30 ck begin point: rising edge of ck - /ck with odt being first registered high end point: extrapolated point at vssq taonpd tsw2 vsw2 vsw1 tsw1 /ck vssq dq, dm dqs, /dqs tdqs, /tdqs vtt vssq b) definition of taonpd ck begin point: rising edge of ck - /ck defined by the end point of odtloff end point: extrapolated point at vrtt_nom vrtt_nom taof tsw2 vsw2 vsw1 tsw1 /ck dq, dm dqs, /dqs tdqs, /tdqs vtt vssq c) definition of taof begin point: rising edge of ck - /ck with odt being first registered low ck end point: extrapolated point at vrtt_nom vrtt_nom taofpd tsw2 vsw2 vsw1 tsw1 /ck dq, dm dqs, /dqs tdqs, /tdqs vtt vssq d) definition of taofpd
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 31 ck begin point: rising edge of ck - /ck defined by the end point of odtlcnw begin point: rising edge of ck - /ck defined by the end point of odtlcwn4 or odtlcwn8 end point: extrapolated point at vrtt_wr tadc tsw21 tsw11 vsw2 tsw12 tsw22 vsw1 /ck tadc vrtt_wr vrtt_nom vrtt_nom dq, dm dqs, /dqs tdqs, /tdqs end point: extrapolated point at vrtt_nom vtt vssq e) definition of tadc
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 32 idd measurement conditions (tc = 0 + = ? ? : : ? : ? : ? : = ? ? : ? ? = ? = = ? = ? ? = : = ? = : =
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 33 idd iddq vddq/2 ddr3 sdram vdd vddq vss vssq cke /cs /ras, /cas, /we address, ba odt zq rtt = 25 ? /reset ck, /ck dqs, /dqs, dq, dm, tdqs, /tdqs measurement setup and test load for idd and iddq measurements application specific memory channel environment channel i/o power simulation channel i/o power number correction correlation iddq measurement iddq simulation iddq test load correlation from simulate d channel i/o power to actual channel i/o power supported by iddq measurement.
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 34 timings used for idd and iddq measurement-loop patterns ddr3l-1600 ddr3l-1333 ddr3l-1066 parameter 11-11-11 9-9-9 7-7-7 unit cl 11 9 7 nck tck min. 1.25 1.5 1.875 ns nrcd min. 11 9 7 nck nrc min. 39 33 27 nck nras min. 28 24 20 nck nrp min. 11 9 7 nck nfaw 24 20 20 nck nrrd 5 4 4 nck nrfc 128 107 86 nck
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 35 basic idd and iddq m easurement conditions parameter symbol description operating one bank active precharge current idd0 cke: h; external clock: on; tck, nrc, nras, cl: see timings used for idd and iddq measurement-loop patterns table; bl: 8* 1 ; al: 0; /cs: h between act and pre; command, address, bank address inputs: partially toggling according to idd0 measurement-loop pattern table; data i/o: floating; dm: stable at 0; bank activity: cycling with one bank active at a time: 0,0,1,1,2,2,... (see idd0 measurement- loop pattern table); output buffer and rtt: enabled in mr* 2 ; odt signal: stable at 0; pattern details: see idd0 measurement-loop pattern table operating one bank active-read-precharge current idd1 cke: h; external clock: on; tck, nrc, nras, nrcd, cl: see timings used for idd and iddq measurement-loop patterns table; bl: 8* 1, 6 ; al: 0; /cs: h between act, read and pre; command, address, bank address inputs, dat a i/o: partially toggling according to idd1 measurement-loop pattern table; dm: stable at 0; bank activity: cycling wi th one bank active at a time: 0,0,1,1,2,2,... (see idd1 measurement-loop pattern table); output buffer and rtt: enabled in mr* 2 ; odt signal: stable at 0; pattern details: see idd1 measurement-loop pattern table precharge standby current idd2n cke: h; external clock: on; tck, cl: see timings used for idd and iddq measurement- loop patterns table bl: 8* 1 ; al: 0; /cs: stable at 1; command, address, bank address inputs: partially toggling according to idd2n and idd3n measurement-loop pattern table; data i/o: floa ting; dm: stable at 0; bank activity: all banks closed; output buffer and rtt: enabled in mode registers* 2 ; odt signal: stable at 0; pattern details: see idd2n and idd3n measurement-loop pattern table precharge standby odt current idd2nt cke: h; external clock: on; tck, cl: see timings used for idd and iddq measurement- loop patterns table; bl: 8* 1 ; al: 0; /cs: stable at 1; command, address, bank address inputs: partially toggling according to idd2nt and iddq2nt measurement-loop pattern table; data i/o: floating; dm: stable at 0; bank activity: all banks closed; output buffer and rtt: enabled in mr* 2 ; odt signal: toggling according to idd2nt and iddq2nt measurement-loop pattern table; pattern details: see idd2nt and iddq2nt measurement-loop pattern table precharge standby odt iddq current iddq2nt same definition like for idd2nt, however measuring iddq current instead of idd current precharge power-down current slow exit idd2p0 cke: l; external clock: on; tck, cl: s ee timings used for idd and iddq measurement- loop patterns table; bl: 8* 1 ; al: 0; /cs: stable at 1; command, address, bank address inputs: stable at 0; data i/o: floating; dm: stable at 0; bank activity: all banks closed; output buffer and rtt: emr * 2 ; odt signal: stable at 0; precharge power down mode: slow exit* 3 precharge power-down current fast exit idd2p1 cke: l; external clock: on; tck, cl: s ee timings used for idd and iddq measurement- loop patterns table; bl: 8* 1 ; al: 0; /cs: stable at 1; command, address, bank address inputs: stable at 0; data i/o: floating; dm:stable at 0; bank activity: all banks closed; output buffer and rtt: enabled in mr* 2 ; odt signal: stable at 0; precharge power down mode: fast exit* 3 precharge quiet standby current idd2q cke: h; external clock: on; tck, cl: s ee timings used for idd and iddq measurement- loop patterns table; bl: 8* 1 ; al: 0; /cs: stable at 1; command, address, bank address inputs: stable at 0; data i/o: floating; dm: stable at 0;bank activity: all banks clos ed; output buffer and rtt: enabled in mr* 2 ; odt signal: stable at 0 active standby current idd3n cke: h; external clock: on; tck, cl : see table timings used for idd and iddq measurement-loop patterns table; bl: 8* 1 ; al: 0; /cs: stable at 1; command, address, bank address inputs: partially toggling according to idd2n and idd3n measurement-loop pattern; data i/o: floating; dm: stable at 0; bank activity: all banks open; output buffer and rtt: enabled in mr* 2 ; odt signal: stable at 0; pattern details: see idd2n and idd3n measurement-loop pattern table active power-down current idd3p cke: l; external clock: on; tck, cl : see table timings used for idd and iddq measurement-loop patterns table; bl: 8* 1 ; al: 0; /cs: stable at 1; command, address, bank address inputs: stable at 0; data i/o: floating; dm:stable at 0; bank activity: all banks open; output buffer and rtt: enabled in mr* 2 ; odt signal: stable at 0
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 36 parameter symbol description operating burst read current idd4r cke: h; external clock: on; tck, cl: s ee timings used for idd and iddq measurement- loop patterns table; bl: 8* 1, 6 ; al: 0; /cs: h between read; command, address, bank address inputs: partially toggling according to idd4r and iddq4r measurement-loop pattern table; data i/o: seamless read data burst with different data between one burst and the next one according to idd4r and iddq4r measurement-loop pattern table; dm: stable at 0; bank activity: all banks open, read commands cycling through banks: 0,0,1,1,2,2,... (see idd4r and iddq4r measurement-loop pattern table); output buffer and rtt: enabled in mr* 2 ; odt signal: stable at 0; pattern details: see idd4r and iddq4r measurement-loop pattern table operating burst read iddq current iddq4r same definition like for idd4r, however measuring iddq current instead of idd current operating burst write current idd4w cke: h; external clock: on; tck, cl: see timings used for idd and iddq measurement- loop patterns table; bl: 8* 1 ; al: 0; /cs: h between wr; command, address, bank address inputs: partially toggling according to idd4w measurement-loop pattern table; data i/o: seamless write data burst with different data between one burst and the next one according to idd4w measurement-loop pattern table; dm: stable at 0; bank activity: all banks open, wr commands cycling through banks: 0,0,1,1,2,2,.. (see idd4w measurement-loop pattern table); output buffer and rtt: enabled in mr* 2 ; odt signal: stable at h; pattern details: see idd4w measurement-loop pattern table burst refresh current idd5b cke: h; external clock: on; tck, cl, nrfc: see timings used for idd and iddq measurement-loop patterns table; bl: 8* 1 ; al: 0; /cs: h between ref; command, address, bank address inputs: partially toggling according to idd5b measurement-loop pattern table; data i/o: floating; dm: stable at 0; bank activity: ref command every nrfc (idd5b measurement-loop pattern); output buffer and rtt: enabled in mr* 2 ; odt signal: stable at 0; pattern details: see idd5b measurement-loop pattern table self-refresh current: normal temperature range idd6 tc: 0 to 85c; asr: disabled* 4 ; srt: normal* 5 ; cke: l; external clock: off; ck and /ck: l; cl: see timings used for idd and iddq measurement-loop patterns table; bl: 8* 1 ; al: 0; /cs, command, address, bank address, data i/o: floating; dm: stable at 0; bank activity: self-refresh operat ion; output buffer and rtt: enabled in mr* 2 ; odt signal: floating self-refresh current: extended temperature range idd6et tc: 0 to 95c; asr: disabled* 4 ; srt: extended* 5 ; cke: l; external clock: off; ck and /ck: l; cl: see timings used for idd and iddq measurement-loop patterns table; bl: 8* 1 ; al: 0; /cs, command, address, bank address, data i/o: floating; dm: stable at 0; bank activity: extended temp erature self-refresh operation; output buffer and rtt: enabled in mr* 2 ; odt signal: floating auto self-refresh current (optional) idd6tc tc: 0 to 95c; asr: enabled* 4 ; srt: normal* 5 ; cke: l; external clock: off; ck and /ck: l; cl: see table timings used for idd and iddq measurement-loop patterns table; bl: 8* 1 ; al: 0; /cs, command, address, bank address, data i/o: floating; dm: stable at 0; bank activity: auto self-refr esh operation; output buffer and rtt: enabled in mr* 2 ; odt signal: floatng operating bank interleave read current idd7 cke: h; external clock: on; tck, nrc, nr as, nrcd, nrrd, nfaw, cl: see timings used for idd and iddq measurement-loop patterns table; bl: 8* 1, 6 ; al: cl-1; /cs: h between act and reada; command, address, bank address inputs: partially toggling according to idd7 measurement-loop pattern table; data i/o: read data bursts with different data between one burst and the next one according to idd7 measurement-loop pattern table; dm: stable at 0; bank activity: two times interleaved cycling through banks (0, 1, ?7) with different addressing, see idd7 measurement-loop pattern table; output buffer and rtt: enabled in mr* 2 ; odt signal: stable at 0; pattern details: see idd7 measurement-loop pattern table reset low current idd8 /reset: low; external clock: off; ck and /c k: low; cke: floating; /cs, command, address, bank address, data io: floating; odt signal: floating reset low current reading is valid once power is stable and /reset has been low for at least 1ms.
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 37 notes: 1. burst length: bl8 fixed by mrs: mr0 bits [1,0] = [0,0]. 2. mr: mode register output buffer enable: set mr1 bit a 12 = 1 and mr1 bits [5, 1] = [0,1]; rtt_nom enable: set mr1 bits [9, 6, 2] = [0, 1, 1]; rtt_wr enable: set mr2 bits [10, 9] = [1,0]. 3. precharge power down mode: set mr0 bit a12= 0 for slow exit or mr0 bi t a12 = 1 for fast exit. 4. auto self-refresh (asr): set mr2 bit a6 = 0 to disable or 1 to enable feature. 5. self-refresh temperature range (srt): set mr0 bit a7= 0 for normal or 1 for extended temperature range. 6. read burst type: nibble sequential, set mr0 bit a3 = 0.
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 38 idd0 measurement-loop pattern notes: 1. dm must be driven low all the time. dqs, /dqs are floating. 2. dq signals are floating. 3. ba: ba0 to ba2. ck, /ck cke sub -loop cycle number com- mand /cs /ras /cas /we odt ba* 3 a11 -a14 a10 a7 -a9 a3 -a6 a0 -a2 data* 2 0 act 0 0 1 1 0 0 0 0 0 0 0 ? ? ? ? ? ? + ? + ? + ? + + ? + ? + ? = = = = = = =
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 39 idd1 measurement-loop pattern notes: 1. dm must be driven low a ll the time. dqs, /dqs are used according to read commands, otherwise floating. 2. burst sequence driven on each dq signal by read command. outside burst operation, dq signals are floating. 3. ba: ba0 to ba2. ck, /ck cke sub -loop cycle number com- mand /cs /ras /cas /we odt ba* 3 a11 -a14 a10 a7 -a9 a3 -a6 a0 -a2 data* 2 0 act 0 0 1 1 0 0 0 0 0 0 0 ? ? ? ? ? ? ? + ? + ? + ? + + ? + + + ? + ? + ? = = = = = = =
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 40 idd2n and idd3n measurement-loop pattern notes: 1. dm must be driven low all the time. dqs, /dqs are floating. 2. dq signals are floating. 3. ba: ba0 to ba2. idd2nt and iddq2nt measurement-loop pattern notes: 1. dm must be driven low all the time. dqs, /dqs are floating. 2. dq signals are floating. 3. ba: ba0 to ba2. ck, /ck cke sub -loop cycle number com- mand /cs /ras /cas /we odt ba* 3 a11 -a14 a10 a7 -a9 a3 -a6 a0 -a2 data* 2 0 d 1 0 0 0 0 0 0 0 0 0 0 ? ? ? ? = = = = = = = ? ? ? ? = = = = = = = = = = = = = =
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 41 idd4r and iddq4r measurement-loop pattern notes: 1. dm must be driven low a ll the time. dqs, /dqs are used according to read commands, otherwise floating. 2. burst sequence driven on each dq signal by read command. outside burst operation, dq signals are floating. 3. ba: ba0 to ba2. ck, /ck cke sub -loop cycle number com- mand /cs /ras /cas /we odt ba* 3 a11 -a14 a10 a7 -a9 a3 -a6 a0 -a2 data* 2 0 read 0 1 0 1 0 0 0 0 0 0 0 00000000 1 d 1 0 0 0 0 0 0 0 0 0 0 ? ? ? ? = = = = = = =
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 42 idd4w measurement-loop pattern notes: 1. dm must be driven low a ll the time. dqs, /dqs are used according to write commands, otherwise floating. 2. burst sequence driven on each dq signal by wr ite command. outside burst operation, dq signals are floating. 3. ba: ba0 to ba2. idd5b measurement-loop pattern notes: 1. dm must be driven low all the time. dqs, /dqs are floating. 2. dq signals are floating. 3. ba: ba0 to ba2. ck, /ck cke sub -loop cycle number com- mand /cs /ras /cas /we odt ba* 3 a11 -a14 a10 a7 -a9 a3 -a6 a0 -a2 data* 2 0 writ 0 1 0 0 1 0 0 0 0 0 0 00000000 1 d 1 0 0 0 1 0 0 0 0 0 0 ? ? ? ? = = = = = = = ? ? ? = = = = = = = ? ?
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 43 idd7 measurement-loop pattern ck, /ck cke sub -loop cycle number com- mand /cs /ras /cas /we odt ba* 3 a11 -a14 a10 a7 -a9 a3 -a6 a0 -a2 data* 2 0 act 0 0 1 1 0 0 0 0 0 0 0 ? ? ? ? + + ? = = ? = + = + = + = ? + + ? + ? + + + ? + + + + + ? + = + = ? + ? = + = + = + = ? + ?
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 44 notes: 1. dm must be driven low all the time. dqs, /d qs are used according to read commands, otherwise floating. 2. burst sequence driven on each dq signal by read command. outside burst operation, dq signals are floating. 3. ba: ba0 to ba2.
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 45 electrical specifications dc characteristics 1 (tc = 0 + =
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 46 self-refresh current (tc = 0 + = ? ?
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 47 pin capacitance (tc = 25 = ? ? ? ? ? ? : = = = ? = ? + = ? + = ? + : ?
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 48 standard speed bins [ddr3l-1600 speed bins] speed bin ddr3l-1600k cl-trcd-trp 11-11-11 symbol /cas write latency min. max. unit notes taa 13.125 20 ns 9 trcd 13.125 ? ? ? = = = = = = = = = = < = = = = = < = = = = = < = = = = < = = = = <
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 49 [ddr3l-1333 speed bins] speed bin ddr3l-1333h cl-trcd-trp 9-9-9 symbol /cas write latency min. max. unit notes taa 13.125 20 ns 9 trcd 13.125 ? ? ? = = = = = = = = = = < = = = = < = = = = < = = = <
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 50 [ddr3l-1066 speed bins] speed bin ddr3l-1066f cl-trcd-trp 7-7-7 symbol /cas write latency min. max. unit notes taa 13.125 20 ns 9 trcd 13.125 ? ? ? = = = = = = = = = < = = = < : : : = : + = =
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 51 ac characteristics (tc = 0 + = = ? : : ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + ? ? ? ? ? ? ? ? ? ? ? ? ?
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 52 -gn -dj data rate (mbps) 1600 1333 parameter symbol min. max. min. max. unit notes dqs latching rising transitions to associated clock edges tdqss ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + + ? + ? ? ? + + ? ? + + ? ? + + ? ? + + ? ? ? ? ? ? ? ? ? ? ? ? + ? + ? ? ? ? ? ? ? ? ? + ? + ? ? ?
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 53 -gn -dj data rate (mbps) 1600 1333 parameter symbol min. max. min. max. unit notes exit self-refresh to commands requiring a locked dll txsdll tdllk (min.) ? ? ? ? + ? ? + < + ? ? ? ? ? ? + ? + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + + ? + + ? + + ? + + ? + + ? + + ? + + + ? + + + ? + + + ? + + + ? ? ? ? ?
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 54 odt ac electrical characte ristics [ddr3l-1600, 1333] -gn -dj data rate (mbps) 1600 1333 parameter symbol min. max. min. max. unit notes rtt turn-on taon ? ? ? ? ? + ? + ? + ? + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ?
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 55 ac characteristics [ddr3l-1066] -ae data rate (mbps) 1066 parameter symbol min. max. unit notes clock cycle time average cl = x tck(avg) 1875 3333 ps minimum clock cycle time (dll-off mode) tck (dll-off) 8 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + ? ? ? ? ? ? ? + ? ? ?
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 56 -ae data rate (mbps) 1066 parameter symbol min. max. unit notes dqs output high time tqsh 0.38 ? ? ? ? ? ? ? ? ? ? + + ? ? + + ? ? + + ? ? ? ? ? ? ? + ? ? ? ? ? + ? ? ? ? + ? + < + ?
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 57 -ae data rate (mbps) 1066 parameter symbol min. max. unit notes cke minimum pulse width (high and low pulse width) tcke 5.625 ? ? + ? ? ? ? ? ? ? ? ? ? + + ? + + ? + + ? + + + ? + + + ? ? ?
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 58 odt ac electrical charac teristics [ddr3l-1066] -ae data rate (mbps) 1066 parameter symbol min. max. unit notes rtt turn-on taon ?300 300 ps 7, 12, 37 asynchronous rtt turn-on delay (power-down with dll frozen) taonpd 2 8.5 ns rtt_nom and rtt_wr turn-off time from odtloff reference taof 0.3 0.7 tck (avg) 8, 12, 37 odt turn-off (power-down mode) taofpd 2 8.5 ns odt to power-down entry/exit latency tanpd wl ? 1 ? ? + ? + ? ? ? ? ? ? ? ? ?
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 59 notes for ac electrical characteristics notes: 1. actual value dependant upon measurement level definitions. s ee figure method for calculating twpre transitions and endpoints and see figure method fo r calculating twpst transitions and endpoints. 2. commands requiring locked dll are: read (and reada) and synchronous odt commands. 3. the max values are system dependent. 4. wr as programmed in mode register. 5. value must be rounded-up to next integer value. 6. there is no maximum cycle time limit besides the need to satisfy the refresh interval, trefi. 7. odt turn on time (min.) is when the device leaves high impedance and odt resistance begins to turn on. odt turn on time (max.) is when the odt resistance is fully on. both are measured from odtlon. 8. odt turn-off time (min.) is when the device starts to turn-off odt resistance. odt turn-off time (max.) is when the bus is in high impedance. both are measured from odtloff. 9. twr is defined in ns, for calculation of twrpden it is necessary to round up twr/tck to the next integer. 10. wr in clock cycles as programmed in mr0. 11. the maximum read postamble is bound by tdqs ck (min.) plus tqsh (min.) on the left side and thz (dqs) (max.) on the right side. see figure clock to data strobe relationship. 12. output timing deratings are rela tive to the sdram input clock. w hen the device is operated with input clock jitter, this parameter needs to be derated by tbd. 13. value is only valid for ron34. 14. single ended signal parameter. refer to the secti on of tlz(dqs), tlz(dq), thz(dqs), thz(dq) notes for definition and meas urement method. 15. trefi depends on operating case temperature (tc). 16. tis(base) and tih(base) values are for 1v/ns command/address single-ended slew rate and 2v/ns ck, /ck differential slew rate. note for dq and dm signals, vref(dc) = vrefdq(dc). for input only pins except /reset, vref(dc) = vrefca(dc). see addr ess / command setup, hold and derating section 17. tds(base) and tdh(base) values are for 1v/n s dq single-ended slew rate and 2v/ns dqs, /dqs differential slew rate. note for dq and dm signals, vref(dc) = vrefdq(dc). for input only pins except /reset, vref(dc) = vrefca(dc). see data set up, hold and slew ra te derating section. 18. start of internal write tr ansaction is definited as follows: for bl8 (fixed by mrs and on- the-fly): rising clock edge 4 clock cycles after wl. for bc4 (on-the-fly): rising clock edge 4 clock cycles after wl. for bc4 (fixed by mrs): rising clock edge 2 clock cycles after wl. 19. the maximum read preamble is bound by tlz(dq s)(min.) on the left side and tdqsck(max.) on the right side. 20. cke is allowed to be registered low while operatio ns such as row activation, precharge, auto precharge or refresh are in progress, but power-down idd spec will not be applied until finishing those operations. 21. although cke is allowed to be registered low afte r a refresh command once trefpden(min.) is satisfied, there are cases where additional time such as txpdll(min.) is also required. see figure power-down entry/exit clarifica tions - case 2. 22. tjit(duty) =
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 60 26. for these parameters, the ddr3 sdram device is characterized and verified to support tnparam [nck] = ru{tparam [ns] / tck(avg)}, which is in clock cycles, assu ming all input clock jitter specifications are satisfied. for example, the device will support tnrp = ru{trp / tc k(avg)}, which is in clock cycles, if all input clock jitter specifications are met. this means: for ddr 3-800 6-6-6, of which trp = 15ns, the device will support tnrp =ru{trp / tck(avg)} = 6, i.e. as long as the input clock jitter specifications are met, precharge command at tm and active co mmand at tm+6 is valid even if (tm+6 ? :

where tsens = max.(drttdt, drondtm) and vs ens = max.(drttdv, drondvm) define the sdram temperature and voltage sensitivities. for example, if tsens = 1.5%/ = = = : 0.5 (1.5 1) + (0.15 15) = 0.133 128ms 31. the tis(base) ac135 s pecifications are adjusted fr om the tis(base) specificat ion by adding an additional 125ps of derating to accommodate for the lower al ternate threshold of 135mv and another 25ps to account for the earlier reference point [(160mv ? ? ? + = + = = ? = + = ? = ? ? = ? = ? = + = + = ? ? = ? = + = + = = ? = + = + = + = ? = + = + = + = ? = +
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 61 clock jitter [ddr3l-1600, 1333] -gn -dj data rate (mbps) 1600 1333 parameter symbol min. max. min. max. unit notes average clock period tck (avg) 1250 3333 1500 3333 ps 1 absolute clock period tck (abs) tck(avg)min + tjit(per)min tck(avg)max+ tjit(per)max tck(avg)min + tjit(per)min tck(avg)max+ tjit(per)max ps 2 clock period jitter tjit (per) ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? = = + = + ? ? ? ? ? ? ? ?
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 62 clock jitter [ddr3l-1066] -ae data rate (mbps) 1066 parameter symbol min. max. unit notes average clock period tck (avg) 1875 3333 ps 1 absolute clock period tck (abs) tck(avg)min + tjit(per)min tck(avg)max+ tjit(per)max ps 2 clock period jitter tjit (per) ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? = = + = + ? ? ? ? : n j = 1 tck j n n = 200 2. tck (abs) is the absolute clock per iod, as measured from one rising e dge to the next consecutive rising edge. tck (abs) is not subject to production test. 3. tch (avg) is defined as the average high pulse width, as calculated across any consecutive 200 high pulses. n j = 1 tch j (n t ck(avg) ) n = 200
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 63 4. tcl (avg) is defined as the average low pulse widt h, as calculated across any consecutive 200 low pulses. n j = 1 tcl j (n t ck(avg) ) n = 200 5. tjit (duty) is defined as the cumulative set of tc h jitter and tcl jitter. tch jitte r is the largest deviation of any single tch from tch (avg). tcl jitter is the la rgest deviation of any single tcl from tcl (avg). tjit (duty) is not subject to production test. tjit (duty) = min./max. of {tjit (ch), tjit (cl)}, where: tjit (ch) = {tch j - tch (avg) where j = 1 to 200} tjit (cl) = {tcl j - tcl (avg) where j = 1 to 200} 6. tjit (per) is defined as the largest dev iation of any single tck from tck (avg). tjit (per) = min./max. of { tck j ? = : = + = + + + + + +
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 64 block diagram bank 7 bank 6 bank 5 bank 4 address, ba0, ba1, ba2 /cs /ras /cas /we command decoder input & output buffer latch circuit data control circuit column decoder row decoder memory cell array bank 0 sense amp. bank 1 bank 2 bank 3 control logic column address buffer and burst counter row address buffer and refresh counter mode register clock generator dq ck /ck cke dqs, /dqs dm dll ck, /ck tdqs, /tdqs odt
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 65 pin function ck, /ck (input pins) ck and /ck are differential clock inputs. all address and c ontrol input signals are sampled on the crossing of the positive edge of ck and negative edge of /ck. output (read) data is referenced to the crossings of ck and /ck (both directions of crossing). /cs (input pin) all commands are masked when /cs is registered high. /cs provides for external rank selection on systems with multiple ranks. /cs is considered part of the command code. /ras, /cas, /we (input pins) /ras, /cas and /we (along with /cs) define the command being entered. a0 to a14 (input pins) provided the row address for active commands and the co lumn address for read/write commands to select one location out of the memory array in the respective bank. (a10(ap) and a12(/bc) have additional functions, see below) the address inputs also provide t he op-code during mode register set commands. [address pins table] address (a0 to a14) part number page size row address (ra) column address (ca) note EDJ2104EDBG 1kb ax0 to ax14 ay0 to ay9, ay11 edj2108edbg ax0 to ax14 ay0 to ay9 a10(ap) (input pin) a10 is sampled during read/write commands to determine whether auto precharge should be performed to the accessed bank after the read/write operation. (h igh: auto precharge; low: no auto precharge) a10 is sampled during a precharge command to determine whether the precharge applies to one bank (a10 = low) or all banks (a10 = high). if only one bank is to be prec harged, the bank is selected by bank addresses (ba). a12(/bc) (input pin) a12 is sampled during read and write commands to determi ne if burst chop (on-the-fly) will be performed. (a12 = high: no burst chop, a12 = low: burs t chopped.) see command truth table for details. ba0 to ba2 (input pins) ba0, ba1 and ba2 define to which bank an active, read, write or precharge command is being applied. ba0 and ba1 also determine which mode register (mr0 to mr3) is to be accessed during a mrs cycle. [bank select signal table] ba0 ba1 ba2 bank 0 l l l bank 1 h l l bank 2 l h l bank 3 h h l bank 4 l l h bank 5 h l h bank 6 l h h bank 7 h h h remark: h: vih. l: vil.
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 66 cke (input pin) cke high activates, and cke low deactivates, internal cl ock signals and device input buffers and output drivers. taking cke low provides precharge power-down and self-refr esh operation (all banks idle), or active power-down (row active in any bank). cke is asynchronous for se lf-refresh exit. after vref has become stable during the power-on and initialization sequence, it must be maintained for proper operat ion of the cke receiver. for proper self-refresh entry and exit, vref must be maintained to this input. cke must be maintained high throughout read and write accesses. input buffers, excluding ck, /ck, odt and cke are disabled during power-down. input buffers, excluding cke, are disabled during self-refresh. dm (input pins) dm is an input mask signal for write data. input data is masked when dm is sampled high coincident with that input data during a write access. dm is sampled on both edges of dqs. for = = = =
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 67 command operation command truth table the ddr3 sdram recognizes the following commands spec ified by the /cs, /ras, /cas, /we and address pins. cke function symbol previous cycle current cycle /cs /ras /cas /we ba0 to ba2 a12 (/bc) a10 (ap) address notes mode register set mrs h h l l l l ba op-code auto-refresh ref h h l l l h v v v v self-refresh entry self h l l l l h v v v v 6, 8, 11 self-refresh exit srex l h h : = = = = = = = =
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 68 notes: 1. all ddr3 commands are defined by states of /c s, /ras, /cas, /we and cke at the rising edge of the clock. the most significant bit (msb) of ba, ra , and ca are device density and configuration dependent. 2. /reset is an active low asynchronous signal that must be driven high during normal operation 3. bank addresses (ba) determine which bank is to be operated upon. for mrs, ba selects an mode register. 4. burst reads or writes cannot be terminated or interrupted and fixed/on the fly bl will be defined by mrs. 5. the power-down mode does not perform any refresh operations. 6. the state of odt does not affe ct the states described in this tabl e. the odt function is not available during self-refresh. 7. self-refresh exit is asynchronous. 8. vref (both vrefdq and vrefca) must be mainta ined during self-refresh oper ation. vrefdq supply may be turned off and vrefdq may take any value between vss and vdd during self-refresh operation, provided that vrefdq is valid and stable prior to cke going back high and that first write operation or first write leveling activity may not occur earlie r than 512 nck after exit from self-refresh. 9. the no operation command (nop) should be used in cases when the ddr3 sdram is in an idle or a wait state. the purpose of the nop command is to prevent the ddr3 sdram from registering any unwanted commands between operations. a nop command will not terminate a previous operation that is still executing, such as a burst read or write cycle. 10. the desl command performs t he same function as a nop command. 11. refer to the cke truth table for more detail with cke transition. 12. no more than 4 banks may be activated in a ro lling tfaw window. converting to clocks is done by dividing tfaw (ns) by tck (ns) and rounding up to next integer value. as an example of the rolling window, if (tfaw/tck) rounds up to 10 clocks, and an activate command is issued in clock n, no more than three further activate commands may be issued in clock n+1 through n+9. no operation command [nop] the no operation command (nop) should be used in cases wh en the ddr3 sdram is in an idle or a wait state. the purpose of the nop command is to prevent the ddr3 sdram from registering any unwanted commands between operations. a nop command will not terminate a previous operation that is still exec uting, such as a burst read or write cycle. the no operation (nop) command is used to instruct the selected ddr3 sdra m to perform a nop (/cs low, /ras, /cas, /we high). this prevents unwanted commands from being registered during idle or wait states. operations already in progress are not affected. device deselect command [desl] the deselect function (/cs high) prevents new comm ands from being executed by the ddr3 sdram. the ddr3 sdram is effectively deselected. operatio ns already in progress are not affected. mode register set command [mr0 to mr3] the mode registers are loaded via row address inputs. see mode register descriptions in the programming the mode register section. the mode register set co mmand can only be issued when all banks are idle, and a subsequent executable command cannot be issued until tmrd is met. bank activate command [act] this command is used to open (or activate) a row in a particu lar bank for a subsequent access. the values on the ba inputs select the bank, and the address provided on row add ress inputs selects the row. this row remains active (or open) for accesses until a precharge command is issu ed to that bank. a precharge command must be issued before opening a different row in the same bank. note: no more than 4 banks may be activated in a rolling tfaw window. converting to clocks is done by dividing tfaw (ns) by tck (ns) and rounding up to next integer value. as an example of the rolling window, if (tfaw/tck) rounds up to 10 clocks, and an activate command is issued in clock n, no more than three further activate commands may be issued in clock n+1 through n+9.
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 69 read command [read, rds4, rds8, reada, rdas4, rdas8] the read command is used to initiate a burst read access to an active row. the values on the ba inputs select the bank, and the address provided on column address inputs sele cts the starting column location. the value on input a10 determines whether or not auto precharge is used. if aut o precharge is selected, the row being accessed will be precharged at the end of the read burs t; if auto precharge is not selected, t he row will remain open for subsequent accesses. write command [writ, wrs4, wrs8, writa, wras4, wras8] the write command is used to initiate a burst write access to an active row. the values on the ba inputs select the bank, and the address provided on column address inputs sele cts the starting column location. the value on input a10 determines whether or not auto precharge is used. if aut o precharge is selected, the row being accessed will be precharged at the end of the write burst; if auto precharge is not selected, the row will remain open for subsequent accesses. input data appearing on the dq is written to the memory array subject to the dm input logic level appearing coincident with the data. if a given dm signal is registered low, the corresponding data will be written to memory; if the dm signal is registered high, the corresp onding data inputs will be ignored, and a write will not be executed to that by te/column location. precharge command [pre, pall] the precharge command is used to deactivate the open row in a particular bank or the open row in all banks. the bank(s) will be available for a subsequent row access a spec ified time (trp) after the precharge command is issued. input a10 determines whether one or all banks are to be precharged, and in t he case where only one bank is to be precharged, inputs ba select the bank. otherwise ba are treated as "don't care." once a bank has been precharged, it is in the idle state and must be activated prior to any read or write commands being issued to that bank. a precharge command will be treated as a nop if ther e is no open row in that bank (idle state), or if the previously open row is already in the process of precharging. auto precharge command [reada, writa] before a new row in an active bank can be opened, the ac tive bank must be precharged using either the precharge command or the auto precharge function. when a read or a write command is given to the ddr3 sdram, the /cas timing accepts one extra address, column address a10, to a llow the active bank to automat ically begin precharge at the earliest possible moment during the bur st read or write cycle. if a10 is low when the read or write command is issued, then normal read or write burst operation is execut ed and the bank remains active at the completion of the burst sequence. if a10 is high when the read or write command is issued, then the auto precharge function is engaged. during auto precharge, a read command will execute as normal with the exception that the active bank will begin to precharge on the rising edge which is (al* + trtp) cycles later from the read with auto precharge command. auto precharge can also be implemented during write co mmands. the precharge operation engaged by the auto precharge command will not begin until the la st data of the burst wr ite sequence is properly stored in the memory array. this feature allows the prec harge operation to be partially or completely hidden during burst read cycles (dependent upon /cas latency) thus improving system performance for random data access. the tras lockout circuit internally delays the precharge operation until the array restore ope ration has been completed so that the auto precharge command may be issued with any read or write command. note: al (additive latenc y), refer to posted /cas de scription in the register definition section. auto-refresh command [ref] auto-refresh is used during normal operation of the ddr3 sdram and is analogous to /cas-before-/ras (cbr) refresh in fpm/edo dram. this command is nonpersistent, so it must be issued each time a refresh is required. the addressing is generated by the internal refresh controller. this makes the address bits a "don't care" during an auto-refresh command. a maximum of eight auto-refresh commands can be posted to any given ddr3, meaning that the maximum absolute interval between any auto-refresh comma nd and the next auto-refresh command is 9
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 70 self-refresh command [self] the self-refresh command can be used to retain data in the ddr 3, even if the rest of the system is powered down. when in the self-refresh mode, the ddr 3 retains data without external clocking. the self-refresh command is initiated like an auto-refresh command except cke is dis abled (low). the dll is automatically disabled upon entering self-refresh and is autom atically enabled and reset upon exiting self -refresh. the active termination is also disabled upon entering self-refresh and enabled upon exiting se lf-refresh. (512 clock cycles must then occur before a read command can be issued). input signals except cke ar e "don't care" during self-refresh. the procedure for exiting self-refresh requires a seque nce of commands. first, ck and /ck must be stable prior to cke going back high. once cke is high, the ddr3 must have nop comm ands issued for txsdll because time is required for the completion of any internal refresh in progress. a simple algorithm for meeting both refresh, dll requirements and out-put calibration is to apply nops for 512 clock cycles before applying any other command to allow the dll to lock and the output drivers to recalibrate. zq calibration command [zqcl, zqcs] zq calibration command (short or long) is used to calibrate dram ron and odt values over pvt. zq calibration long (zqcl) command is used to perform the initial calibration during power-up initialization sequence. zq calibration short (zqcs) command is used to perform pe riodic calibrations to account for vt variations. all banks must be precharged and trp met before zqcl or zqcs commands are issued by the controller. zq calibration commands can also be issued in paralle l to dll lock time when coming out of self-refresh.
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 71 cke truth table cke current state* 2 previous cycle (n-1)* 1 current cycle (n) *1 command (n) *3 /cs, /ras, /cas, /we operation (n) *3 notes power-down l l : = = = : ? + +
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 72 simplified state diagram power on reset procedure power applied reset from any state initialization zq calibration idle activating mrs, mpr, write leveling self refresh refreshing mrs self selfx cke_l cke_l cke_l ref pden pdex act precharge power down active power down reading writing bank active read read writ writ precharging pden pdex reading writing reada writa reada reada writa writ writa pre, pall automatic sequence command sequence pre, pall pre, pall read zqcl zqcs
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 73 reset and initialization procedure power-up and initialization sequence 1. apply power (/reset is recommended to be maintained below 0.2 > ? < ? ? ? ? ? ? =
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 74 max. (10 ns; 5tck) 10ns tis tis tis 200 s 500 s notes: 1. from time point "td" until "tk", nop or desl commands must be applied between mrs and zqcal commands. 2. txpr = max. (txs; 5tck) : vih or vil ck, /ck vdd, vddq /reset cke command ba odt dram_rtt mrs * 1 mrs mrs mrs zqcal mr2 mr3 mr1 mr0 ta tb tc td te tf tg th ti tj tk txpr tmrd tzqinit tdllk tmrd tmrd tmod * 2 tcksrx reset and initialization sequence at power-on ramping reset and initialization with stable power the following sequence is required for /reset at no power interruption initialization. 1. assert /reset below 0.2 max. (10 ns; 5tck) 10ns tis tis tis 100ns 500 s notes: 1. from time point "td" until"tk", nop or desl commands must be applied between mrs and zqcl commands. 2. txpr = max. (txs; 5tck) : vih or vil ck, /ck vdd, vddq /reset cke command ba odt dram_rtt mrs * 1 mrs mrs mrs zqcl mr2 mr3 mr1 mr0 ta tb tc td te tf tg th ti tj tk txpr tmrd tzqinit tdllk tmrd tmrd tmod * 2 tcksrx reset procedure at power stable condition
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 75 programming the mode register for application flexibility, various func tions, features and modes are programmabl e in four mode registers, provided by the ddr3 sdram, as user defined variables, and they must be programmed via a mode register set (mrs) command. as the default values of the mode registers (mr#) are not defined, content of mode registers must be fully initialized and/or re-initial ized, i.e. written, after power-up and/or rese t for proper operation. also the contents of the mode registers can be altered by re-executing the mrs command during normal operation. when programming the mode registers, even if the user chooses to modify only a sub-set of the mrs fields, all address fields within the accessed mode register must be redefined when the mrs command is issued. mrs command and dll reset does not affect array contents, which means these commands can be executed any time after power-up without affecting the array contents. the mode register set command cycle time, tmrd is required to complete the write operation to the mode register and is the minimum time required between two mrs commands. the mrs command to non-mrs command delay, tmod, is required for the dram to update the features exc ept dll reset and is the minimum time required from an mrs command to a non-mrs command excluding nop and desl. the mode register contents can be changed using the same command and timing requirements during normal operation as long as the dra m is in idle state, i.e. all banks are in the precharged state with trp satisfied, all data bursts are comp leted and cke is already high prior to writing into the mode register. the mode registers are divided into various fields depending on the functionality and/or modes. mode register set command cycle time (tmrd) tmrd is the minimum time required from an mrs comm and to the next mrs command. as dll enable and dll reset are both mrs commands, tmrd is applicable between mrs to mr1 for dll enable and mrs to mr0 for dll reset, and not tmod. command mrs nop mrs nop tmrd ck /ck tmrd timing mrs command to non-mrs command delay (tmod) tmod is the minimum time required from an mrs command to a non-mrs command excluding nop and desl. note that additional restrictions may apply, for ex ample, mrs to mr0 for dll reset followed by read. command mrs nop non-mrs nop old setting tmod updating new setting ck /ck tmod timing
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 76 ddr3 sdram mode register 0 [mr0] the mode register mr0 stores t he data for controlling various oper ating modes of ddr3 sdram. it controls burst length, read burst ty pe, /cas latency, test mode, dll re set, wr and dll control for precharge power-down, which include various vendor specific options to make ddr3 sdram useful for various applications. the mode register is written by asserting low on /cs, /r as, /cas, /we, ba0 and ba1, while controlling the states of address pins according to the table below. notes: 1. ba2, a13 and a14 are reserved for future use and must be programmed to 0 during mrs. 2. wr (min.) (write recovery for autoprecharge) is determined by tck (max.) and wr (max.) is determined by tck (mi n.). wr in clock cycles is calculated by dividing twr (in ns) by tck (in ns) and rounding up to the next integer (wr (min.) [cycles] = roundup twr (ns) / tck (ns)). (the wr value in the mode register must be programmed to be equal or larger than wr (min.) this is also used with trp to determine tdal. 0 ppd ba0 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 address field 0 ba1 0 * 1 ba2 0 * 1 a13 wr a8 0 1 dll reset no yes dll tm /cas latency rbt cl bl mode register 0 a7 0 1 mode normal test a6 0 0 0 0 1 1 1 1 /cas latency a5 0 0 1 1 0 0 1 1 a4 0 1 0 1 0 1 0 1 latency reserved 5 6 7 8 9 10 11 a2 0 0 0 0 0 0 0 0 a3 0 1 read burst type nibble sequential interleave a12 0 1 dll control for precharge pd slow exit (dll off) fast exit (dll on) burst length a11 0 0 0 0 1 1 1 1 write recovery for autoprecharge a10 0 0 1 1 0 0 1 1 a9 0 1 0 1 0 1 0 1 wr reserved 5 * 2 6 * 2 7 * 2 8 * 2 10 * 2 12 * 2 reserved ba1 0 0 1 1 mrs mode mr0 mr1 mr2 mr3 ba0 0 1 0 1 a1 0 0 1 1 bl 8 (fixed) 4 or 8 (on the fly) 4 (fixed) reserved a0 0 1 0 1 a14 mr0 programming
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 77 ddr3 sdram mode register 1 [mr1] the mode register mr1 stores the dat a for enabling or disabling the dll, output driver st rength, rtt_nom impedance, additive latency, write leveling enable, tdqs enab le and qoff. the mode register 1 is written by asserting low on /cs, /ras, /cas, /we, high on ba0 and lo w on ba1, while controlling the states of address pins according to the table below. notes: 1. ba2, a8, a10, a13 and a14 are reserved for future use (rfu) and must be programmed to 0 during mrs. 2. outputs disabled - dq, dqs, /dqs. 3. rzq = 240 ? 4. if rtt_nom is used during writes, only the values rzq/2, rzq/4 and rzq/6 are allowed. 5. in write leveling mode (mr1[bit7] = 1) with mr1[bit12] = 1, all rtt_nom settings are allowed; in write leveling mode (mr1[bit7] = 1) with mr1[bit12] = 0, only rtt_nom settings of rzq/2, rzq/4 and rzq/6 are allowed ba0 ba1 a12 a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 address field 1 a14 0 * 1 0 ba2 0 * 1 0 * 1 0 * 1 level rtt_nom d.i.c al rtt_nom rtt_nom d.i.c dll mode register 1 a11 0 1 tdqs enable disabled enabled a0 0 1 dll enable enable disable a6 0 0 1 1 0 0 1 1 a9 0 0 0 0 1 1 1 1 a2 0 1 0 1 0 1 0 1 rtt_nom* 5 odt disabled rzq/4 rzq/2 rzq/6 rzq/12 * 4 rzq/8 * 4 reserved reserved a1 0 1 0 1 a5 0 0 1 1 output driver impedance control rzq/6 rzq/7 reserved reserved tdqs qoff a12 0 1 qoff output buffers enabled output buffers disabled * 2 a7 0 1 write leveling enable disabled enabled a4 0 0 1 1 additive latency 0 (al disabled) cl-1 cl-2 reserved a3 0 1 0 1 a13 mr1 programming
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 78 ddr3 sdram mode register 2 [mr2] the mode register mr2 stores the data for controlling refresh related features, rtt_wr impedance and /cas write latency (cwl). the mode register 2 is written by asserting low on /cs, /r as, /cas, /we, high on ba1 and low on ba0, while con-trolling the states of addre ss pins according to the table below. address field a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 ba1 ba2 ba0 a12 0* 1 mode register 2 0* 1 0* 1 2 pasr* srt rtt_wr* 2 0 1 asr cwl a13 notes: 1. ba2, a8, and a11 to a14 are rfu and must be programmed to 0 during mrs. 2. the rtt_wr value can be applied during writes even when rtt_nom is desabled. during write leveling, dynamic odt is not available. 3. optional in ddr3 sdram: if pasr (partial array self-refresh) is enabled, data located in areas of the array be yond the specified address range will be lost if self-refresh is entered. data integrity will be maintained if tref conditions are met and no self-refresh command is issued. a1 0 0 1 1 0 0 1 1 a2 0 0 0 0 1 1 1 1 full half : bank 0 to bank 3 quarter: bank 0 and bank 1 1/8 : bank 0 3/4 : bank 2 to bank 7 half : bank 4 to bank 7 quarter: bank 6 and bank 7 1/8 : bank 7 a0 0 1 0 1 0 1 0 1 ? (ba [2:0] = 000, 001, 010, 011) (ba [2:0] = 000, 001) (ba [2:0] = 000) (ba [2:0] = 010, 011, 100, 101,110 ,111) (ba [2:0] = 100, 101, 110, 111) (ba [2:0] = 110, 111) (ba [2:0] = 111) partial array self-refresh refresh array a7 0 self-refresh range normal self-refresh extend temperature self-refresh a6 0 1 auto self-refresh method manual sr reference (srt) asr enable (optional) a5 0 0 0 0 1 1 1 1 a4 0 0 1 1 0 0 1 1 a3 0 1 0 1 0 1 0 1 cas write latency (cwl) 5 (tck 2.5ns) 6 (2.5ns > tck 1.875ns) 7 (1.875ns > tck 1.5ns) 8 (1.5ns > tck 1.25ns) reserved reserved reserved reserved a9 0 1 0 1 a10 0 0 1 1 rtt_wr dynamic odt off (write does not affect rtt value) rzq/4 rzq/2 reserved 1 a14 mr2 programming
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 79 ddr3 sdram mode register 3 [mr3] the mode register mr3 controls multi purpose registers (mpr). the mode register 3 is written by asserting low on /cs, /ras, /cas, /we, high on ba1 and ba0, while contro lling the states of address pi ns according to the table below. mode register 3 0* 1 1 1 address field a11 a10 a9 a8 a7 a6 a5 a4 a3 a2 a1 a0 ba1 ba2 ba0 a12 mpr mpr loc a13 n otes : 1. ba2, a3 to a14 are reserved for future use (rfu) and must be programmed to 0 during mrs. 2. the predefined pattern will be used for read synchronization. 3 . when mpr control is set for normal operation, mr3 a[2]=0, mr3 a[1:0] will be ignored. a2 0 1 mpr normal operation * 3 data flow from mpr a1 0 0 1 1 mpr location predefined pattern * 2 rfu rfu rfu a0 0 1 0 1 mpr address mpr operation a14 0* mr3 programming
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 80 burst length (mr0) read and write accesses to the ddr3 are burst oriented, with the burst length being programmable, as shown in the figure mr0 programming. the burst length determines t he maximum number of column locations that can be accessed for a given read or write command. burst length opt ions include fixed bc4, fixed bl8, and on the fly which allows bc4 or bl8 to be selected coincident with the registration of a read on wr ite command via a12 (/bc). reserved states should not be used, as unknown operation or incompatibility with future versions may result. burst chop in case of burst length being fixed to 4 by mr0 setting, the in ternal write operation starts two clock cycles earlier than for the bl8 mode. this means that the starting point for tw r and twtr will be pulled in by two clocks. in case of burst length being selected on the fly via a12(/bc), the inter nal write operation starts at the same point in time like a burst of 8 write operation. th is means that during on-the-fl y control, the starting point for twr and twtr will not be pulled in by two clocks. burst type (mr0) [burst length and sequence] burst length operation starting address (a2, a1, a0) sequential addressing (decimal) interleave addressing (decimal) 4 (burst chop) read 000 0, 1, 2, 3, t, t, t, t 0, 1, 2, 3, t, t, t, t 001 1, 2, 3, 0, t, t, t, t 1, 0, 3, 2, t, t, t, t 010 2, 3, 0, 1, t, t, t, t 2, 3, 0, 1, t, t, t, t 011 3, 0, 1, 2, t, t, t, t 3, 2, 1, 0, t, t, t, t 100 4, 5, 6, 7, t, t, t, t 4, 5, 6, 7, t, t, t, t 101 5, 6, 7, 4, t, t, t, t 5, 4, 7, 6, t, t, t, t 110 6, 7, 4, 5, t, t, t, t 6, 7, 4, 5, t, t, t, t 111 7, 4, 5, 6, t, t, t, t 7, 6, 5, 4, t, t, t, t write 0vv 0, 1, 2, 3, x, x, x, x 0, 1, 2, 3, x, x, x, x 1vv 4, 5, 6, 7, x, x, x, x 4, 5, 6, 7, x, x, x, x 8 read 000 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 001 1, 2, 3, 0, 5, 6, 7, 4 1, 0, 3, 2, 5, 4, 7, 6 010 2, 3, 0, 1, 6, 7, 4, 5 2, 3, 0, 1, 6, 7, 4, 5 011 3, 0, 1, 2, 7, 4, 5, 6 3, 2, 1, 0, 7, 6, 5, 4 100 4, 5, 6, 7, 0, 1, 2, 3 4, 5, 6, 7, 0, 1, 2, 3 101 5, 6, 7, 4, 1, 2, 3, 0 5, 4, 7, 6, 1, 0, 3, 2 110 6, 7, 4, 5, 2, 3, 0, 1 6, 7, 4, 5, 2, 3, 0, 1 111 7, 4, 5, 6, 3, 0, 1, 2 7, 6, 5, 4, 3, 2, 1, 0 write vvv 0, 1, 2, 3, 4, 5, 6, 7 0, 1, 2, 3, 4, 5, 6, 7 remark: t: output driver for dat a and strobes are in high impedance. v: a valid logic level (0 or 1), but res pective buffer input ignores level on input pins. x: don?t care. notes: 1. page length is a function of i/o organization and column addressing 2. 0...7 bit number is value of ca [2:0] that c auses this bit to be the first read during a burst.
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 81 dll enable (mr1) the dll must be enabled for normal operation. dll ena ble is required during power-up initialization, and upon returning to normal operation after having the dll disabled. the dll is automatically disabled when entering self- refresh operation and is automatically re-enabled upon exit of self-refresh oper ation. any time the dll is enabled and subsequently reset, tdllk clock cycles must occur before a read or synchronous odt command can be issued to allow time for the internal clock to be synchronized with t he external clock. failing to wait for synchronization to occur may result in a violation of the tdqsck, taon or taof parameters. during tdllk, cke must continuously be registered high. ddr3 sdram does not require dll for any write operation. ddr3 does not require dll to be locked prior to any write operation. ddr3 requires dll to be locked only fo r read operation and to achieve synchronous odt timing. dll-off mode ddr3 dll-off mode is entered by setting mr1 bit a0 to 1; th is will disable the dll for subsequent operations until a0 bit set back to 0. the mr1 a0 bit for dll control can be switched either during initialization or later. the dll-off mode operations listed below are an optional feature for ddr3. the maximum clock frequency for dll- off mode is specified by the param eter tckdll_off. there is no mini mum frequency limit besides the need to satisfy the refresh interval, trefi. due to latency counter and timing restrictions, only one value of /cas latency (cl) in mr0 and cas write latency (cwl) in mr2 are supported. the dll-off mode is only required to support setting of both cl = 6 and cwl = 6. dll-off mode will affect the read data clock to data strobe relationship (tdqsck) but not the data strobe to data relationship (tdqsq, tqh, tqhs). special attention is needed to line up read data to controller time domain. comparing with dll-on mode, where tdqsck starts from the rising clock edge (al + cl) cycles after the read command, the dll-off mode tdqsck starts (al + cl ? = : ck, /ck command ba dqsdiff_dll-on dq_dll-on dqsdiff_dll-off dq_dll-off dqsdiff_dll-off dq_dll-off read a ca0 ca1 ca2 ca3 ca4 ca5 ca6 ca7 t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 rl = al + cl = 6 (cl = 6, al = 0) rl (dll-off) = al + (cl - 1) = 5 tdqsck(dll-off)_min tdqsck(dll-off)_max cl = 6 ca0 ca1 ca2 ca3 ca4 ca5 ca6 ca7 ca1 ca2 ca3 ca4 ca5 ca6 ca7 ca0 dll-off mode read timing operation
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 82 dll on/off switching procedure ddr3 dll-off mode is entered by setting mr1 bit a0 to ?1?; this will disable the dll for subsequent operations until a0 bit set back to ?0?. dll ?on? to dll ?off? procedure to switch from dll ?on? to dll ?off? requires the frequency to be changed during self-refresh outlined in the following procedure: 1. starting from idle state (all ban ks pre-charged, all timings fulfilled, a nd drams on-die termination resistors, rtt, must be in high impedance state before mrs to mr1 to disable the dll.) 2. set mr1 bit a0 to ?1? to disable the dll. 3. wait tmod. 4. enter self-refresh mode; wa it until (tcksre) satisfied. 5. change frequency, in guidance with input clock frequency change during precharge power-down section. 6. wait until a stable clock is available for at least (t cksrx) at dram inputs. afte r stable clock, wait tcksrx before issuing srx command. 7. starting with the self-refresh exit co mmand, cke must continuously be registered high until all tmod timings from any mrs command are satisfied. in addition, if any odt features were enabled in the mode registers when self- refresh mode was entered, the odt signal must continuously be registered lo w until all tmod timings from any mrs command are satisfied. if both odt features were disabled in the mode registers when self-refresh mode was entered, odt signal can be registered low or high. 8. wait txs, then set mode register s with appropriate values (especially an update of cl, cwl and wr may be necessary. a zqcl command may also be issued after txs). 9. wait for tmod, then dram is ready for next command. ta tb tc tc+1 tc+2 te td tf tf+2 tf+1 tg tg+1 th ck command cke odt /ck mrs sre nop srx mrs valid change frequency tckesr tmod tcksre tcksrx txs tmod dll switch sequence from dll-on to dll-off
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 83 dll ?off? to dll ?on? procedure to switch from dll ?off? to dll ?on? (with required frequency change) during self-refresh: 1. starting from idle state (all banks pre-charged, all timi ngs fulfilled and drams on-die termination resistors (rtt) must be in high impedance state bef ore self-refresh mode is entered.) 2. enter self-refresh mode, wait until tcksre satisfied. 3. change frequency, in guidance with input clock frequency change during precharge power-down section. 4. wait until a stable clock is availabl e for at least (tcksrx) at dram inputs. 5. starting with the self-refresh exit command, cke must continuously be registered high until all tdllk timing from subsequent dll reset command is satisfied. in additi on, if any odt features were enabled in the mode registers when self-refresh mode was ent ered, the odt signal must continuous ly be registered low until tdllk timings from subsequent dll reset command is satisfi ed. if both odt features are disabled in the mode registers when self-refresh mode was entered, odt signal can be registered low or high. 6. wait txs, then set mr1 bit a0 to ?0? to enable the dll. 7. wait tmrd, then set mr0 bit a8 to ?1? to start dll reset. 8. wait tmrd, and then set mode regi sters with appropriate values (especially an update of cl, cwl and wr may be necessary. after tmod is satisfied from any pr oceeding mrs command, a zqcl command may also be issued during or after tdllk.) 9. wait for tmod, and then dram is ready for next command (remember to wait tdllk after dll reset before applying command requiring a locked dll). in addition, wait also for tzqoper in case a zqcl command was issued. ck command cke odt /ck ta tb tc tc+1tc+2 te td tf tf+2 tf+1 tg valid mrs mrs mrs srx nop sre change frequency tckesr odtloff + 1x tck tcksre tcksrx tdllk txs tmrd tmrd dll switch sequence from dll-off to dll-on
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 84 additive latency (mr1) a posted /cas read or write command when issued is held for the time of the additive latency (al) before it is issued inside the device. the read or write posted /cas command may be issued with or without auto precharge. the read latency (rl) is controlled by the sum of al and the /cas latency (cl). the value of al is also added to compute the overall write latency (wl). mrs (1) bits a4 and a3 are used to enable additive latency. mrs1 a4 a3 al* 0 0 0 (posted cas disabled) 0 1 cl ? ? : ? ?
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 85 write leveling (mr1) for better signal integrity, ddr3 memory module adopts fly by topology for the commands, addresses, control signals and clocks. the fly by topology has benefits fo r reducing number of stubs a nd their length but in other aspect, causes flight time skew between clock and strobe at every dram on dimm. it makes controller hard to maintain tdqss, tdss and tdsh specificat ion. therefore, the c ontroller should support ?write leveling? in ddr3 sdram to compensate the skew. write leveling is a scheme to adjust dqs to ck relationship by the controller, with a simple feedback provided by the dram. the memory controller involved in the leveling mu st have adjustable delay setting on dqs to align the rising edge of dqs with that of the clock at the dram pin. dram asynchronously feeds back ck, sampled with the rising edge of dqs, through the dq bus. the c ontroller repeatedly delays dqs until a transition from 0 to 1 is detected. the dqs delay established through this exercise would ensure tdqss, tdss and tdsh specification. a conceptual timing of this scheme is shown as below. diff_clock source destination push dqs to capture 0-1 transition diff_dqs diff_clock diff_dqs dq dq x0 0 x1 1 write leveling concept dqs, /dqs driven by the controller during leveling mode must be terminated by the dram, based on the ranks populated. similarly, the dq bus driven by t he dram must also be terminated at the controller. one or more data bits should carry the leveling feed back to the controller acro ss the dram configurations : : = = = =
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 86 write leveling procedure memory controller initiates leveling mode of all drams by setting bit 7 of mr1 to 1. since the controller levelizes rank at a time, the output of other rank must be disabled by setting mr 1 bit a12 to 1. controller may assert odt after tmod, time at which dram is ready to accept the odt signal. controller may drive dqs low and /dqs high after a del ay of twldqsen, at which time dram has applied on-die termination on these signals. after twlmrd, controller pr ovides a single dqs, /dqs edge which is used by the dram to sample ck driven from controller. twlmrd timing is controller dependent. dram samples ck status with rising ed ge of dqs and provides feedback on all the dq bits asynchronously after twlo timing. there is a dq output unce rtainty of twloe defined to allow mism atch on dq bits; there are no read strobes (dqs, /dqs) needed for these dqs. controller samples incoming dq and decides to increment or decrement dqs delay setting and launches the next dqs, /dqs pulse after some time, which is controller dependent. once a 0 to 1 transition is detected, the controller locks dqs delay setting and write le veling is achieved for the device. the below figure describes detailed timing diagr am for overall procedure and the timing parameters are shown in below figure. /ck ck command odt diff_dqs* 4 all dqs* 1 notes:1. ddr3 sdram drives leveling feedback on all dqs. 2. mrs : load mr1 to enter write leveling mode. 3. nop : nop or deselec 4. diff_dqs is the differential data strobe (dqs, /dqs). timing reference points are the zero crossing. dqs is shown with solid line, /dqs is shown with dotted line. 5. ck, /ck : ck is shown with solid dark line, where as /ck is drawn with dotted line. 6. dqs needs to fulfill minimum pulse width requirements tdqsh (min.) and tdqsl (min.) as defined for regular writes; the max pulse width is system dependent. tmod t1 t2 twlo twlh twls twlmrd twlo twloe tdqsl (min.) tdqsh (min.) tdqsl (min.) tdqsh (min.) twldqsen mrs * 2 nop * 4 nop nop nop nop nop nop nop nop nop nop * 3 twlh twls * 5 * 2 * 3 * 6 * 6 timing details write leveling sequence
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 87 write leveling mode exit the following sequence describes how the write leveling mode should be exited: 1. after the last rising strobe edge(se e t111), stop driving the strobe signals (see ~t128). note: from now on, dq pins are in undefined driving mode, and will remain un defined, until tmod after the respective mr command (t145). 2. drive odt pin low (tis must be satisfied) and continue registering low (see t128). 3. after the rtt is switched off: disable write level mode via mr command (see t132). 4. after tmod is satisfied (t145), any valid commands may be registered. (mr commands may already be issued after tmrd (t136). ck, /ck rtt_dqs-/dqs rtt_dq odt dqs-/dqs dq t111 t112 t116 t117 t128 t131 t132 t136 t145 todtl_off tmrd tmod tis twlo + twloe command ba wl_off mrs 1 result = 1 valid valid valid valid timing details write leveling exit
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 88 tdqs, /tdqs function (mr1) tdqs (termination data st robe) is a feature of = :
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 89 extended temperature usage (mr2) [mode register description] field bits description description asr a6 0 manual sr reference (srt) 1 asr enable (optional) auto self-refresh (asr) (optional) when enabled, ddr3 sdram automatically provides self-refresh power management functions for all supported operating temperature values. if not enabled, the srt bit must be programmed to indicate tc during subsequent self-refresh operation srt a7 0 normal operating temperature range 1 extended operating temperature range self-refresh temperature (srt) range if asr = 0, the srt bit must be programmed to indicate tc during subsequent self-refresh operation if asr = 1, srt bit must be set to 0 partial array self-refresh (pasr) optional in ddr3 sdram: users should refer to the dr am supplier data sheet and/or the dimm spd to determine if ddr3 sdram devices support the followi ng options or requirements referred to in this material. if pasr (partial array self-refresh) is enabled, data located in areas of the array beyond the specified address range shown in figure of mr2 programming will be lost if self-refresh is entered. data integrity will be maintained if trefi conditions are met and no self-refresh command is issued. /cas write latency (cwl) the /cas write latency is defined by mr2 bits [a3, a5 ], as shown in figure of mr2 programming. /cas write latency is the delay, in clock cycles, between the internal wr ite command and the availability of the first bit of input data. ddr3 sdram does not support any half-clock latencies. the overall write latency (wl) is defined as additive latency (al) + /cas write latency (cwl); wl = al + cwl. for more information on the sup-ported cwl and al settings based on the operating clock frequency, refer to ?standard speed bins?. for detailed write operation refer to ?write operation?. auto self-refresh mode - asr mode (optional) ddr3 sdram provides an auto self-refresh mode (asr) for application ease. asr mode is enabled by setting mr2 bit a6 = 1 and mr2 bit a7 = 0. the dram will manag e self-refresh entry in either the normal or extended (optional) temperature ranges. in th is mode, the dram will also manage se lf-refresh power consumption when the dram operating temperature changes, lower at low te mperatures and higher at high temperatures. if the asr option is not supported by the dram, mr2 bit a6 must be set to 0. if the asr mode is not enabled (mr2 bit a6 = 0), the sr t bit (mr2 a7) must be manually programmed with the operating temperature range required during self-refresh operation. support of the asr option does not automatically imply support of the extended temperature range. self- refresh temperature range - srt if asr = 0, the self-refresh temperature (srt) range bi t must be programmed to guarantee proper self-refresh operation. if srt = 0, then the dram will set an appropriate refresh rate for self-refresh operation in the normal temperature range. if srt = 1 then the dram will set an a ppropriate, potentially different, refresh rate to allow self-refresh operation in either the normal or extended te mperature ranges. the value of the srt bit can effect self-refresh power consumption, please refer to the idd table for details. for parts that do not support the exte nded temperature range, mr2 bit a7 must be set to 0 and the dram should not be operated outside the normal temperature range.
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 90 [self-refresh mode summary] mr2 a6 a7 self-refresh operation allowed operating temperature range for self-refresh mode 0 0 self-refresh rate appropriate for the normal temperature range normal (0 + + + +
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 91 multi purpose register (mr3) the multi purpose register (mpr) function is used to re ad out predefined system timing calibration bit sequence.

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conceptual block diagram of multi purpose register to enable the mpr, a mode register set (mrs) command must be issued to mr3 register with bit a2 = 1. prior to issuing the mrs command, all banks must be in the idle state (all banks precharged and trp/trpa met). once the mpr is enabled, any subsequent read or reada commands will be redirected to the multi purpose register. the resulting operation when a read or reada command is iss ued is defined by mr3 bits [a1: a0] when the mpr is enabled. when the mpr is enabled, only read or reada commands are allowed until a subsequent mrs command is issued with the mpr disabled (mr3 bit a2=0 ). power-down mode, self -refresh, and any other non- read/reada command are not allowed during mpr enable mode. the /reset function is supported during mpr enable mode. [functional description of mr3 bits for mpr] mr3 a2 a [1:0] mpr mpr-loc function notes 0 don?t care (0 or 1) normal operation, no mpr transaction. all subsequent reads will come from dram array. all subsequent writes will go to dram array. 1 mr3 a [1:0] enable mpr mode, subsequent read/reada commands defined by mr3 a [1:0] bits. 1 note: 1. see available data locations and burst order bit mapping for multi purpose register table
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 92 ? ? : : ? : : : ? : ? :: ? :: : ? : = : = : ? :: ? : ? : ? : ? : ? : = ? ? ? ? :
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 93 functional block diagrams figures below provide functional block di agrams for the multi purpose register in memory array copy to dq[3:0] q mpr 32 read path dq[3:0] nibblelane 8 4 8 4 8 dm dqs /dqs functional block diagram of multi purpose register in memory array copy to dq[7:0] q mpr 64 read path dq[7:0] bytelane 8 8 8 8 8 dm dqs /dqs functional block diagram of multi purpose register in
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 94 register address table the table below provides an overview of the available data locations, how they are addressed by mr3 a [1:0] during a mr0 to mr3, and how their individual bits are mapped in to the burst order bits dur ing a multi purpose register read. [available data locations and burst order bit mapping for multi purpose register] note: 1. burst order bit 0 is assigned to lsb and burst or der bit 7 is assigned to msb of the selected mpr agent. relevant timing parameters the following ac timing parameters are important for opera ting the multi purpose register: trp, tmrd, tmod and tmprr. besides these timings, all other timing parameters need ed for proper operation of the ddr3 sdram need to be observed. [mpr recovery time tmprr] symbol description tmprr multi purpose register recovery time, def ined between end of mpr read burst and mrs which reloads mpr or disables mpr function mr3 a [2] mr3 a [1:0] function burst length read address a [2:0] burst order and data pattern notes bl8 000 burst order 0,1,2,3,4,5,6,7 pre-defined pattern [0,1,0,1,0,1,0,1] 1 bc4 000 burst order 0,1,2,3, pre-defined pattern [0,1,0,1] 1 1 00 read predefined pattern for system calibration bc4 100 burst order 4,5,6,7 pre-defined pattern [0,1,0,1] 1 bl8 000 burst order 0,1,2,3,4,5,6,7 1 bc4 000 burst order 0,1,2,3 1 1 01 rfu bc4 100 burst order 4,5,6,7 1 bl8 000 burst order 0,1,2,3,4,5,6,7 1 bc4 000 burst order 0,1,2,3 1 1 10 rfu bc4 100 burst order 4,5,6,7 1 bl8 000 burst order 0,1,2,3,4,5,6,7 1 bc4 000 burst order 0,1,2,3, 1 1 11 rfu bc4 100 burst order 4,5,6,7 1
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 95 protocol examples protocol example: read out predetermined read-calibration pattern multiple reads from multi purpose register, in order to do system level read timing calibration based on predetermined and standardized pattern. protocol steps: ? ? ? = : = ? ? = ? : ? : = ? = ? = ? : : ? = + ? ? ? = : = ? ? ? 3 3 valid 1 0 0 * 2 00 00 valid 1 0 valid 0 0 valid * 1 0 0 valid 0 0 valid 0 valid 0 * 2 tmod * 1 tmrd rl notes: 1. read with bl8 either by mrs or otf 2. memory control must drive 0 on a[2:0] vih or vil ck command ba a[1:0] a[2] a[9:3] a10(ap) a[11] a12(/bc) a[15:13] dqs, /dqs dq tmprr pall mrs nop nop read nop mrs nop t0 t4 t5 t9 t17 t18 t19 t20 t21 t22 t23 t24 t25 t26 t27 t28 t29 t30 t31 t39 trp tmod 0 /ck mpr readout of predefined pattern, bl8 fixed burst order, single readout
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 96 tmod * 1 tmrd rl rl notes: 1. read with bl8 either by mrs or otf 2. memory control must drive 0 on a[2:0] vih or vil ck command ba a[1:0] a[2] a[9:3] a10, ap a[11] a12(/bc) a[15:13] dqs, /dqs dq tmprr pall mrs nop nop read mrs nop * 1 read nop nop t0 t4 t5 t9 t17 t18 t19 t20 t21 t22 t23 t24 t25 t26 t27 t28 t29 t30 t31 t43 trp tccd tmod 3 3 valid valid 00 00 valid valid 0 1 0 valid valid 0 0 valid valid * 1 * 1 0 0 valid valid 0 0 valid valid 0 valid 0 * 2 0 * 2 1 0 0 * 2 0 * 2 /ck mpr readout of predefined pattern, bl8 fixed burst order, back-to-back readout t0 t4 t5 t9 t17 t18 t19 t20 t21 t22 tmod * 1 * 1 * 1 tmrd 3 3 valid 0 valid 0 1 0 0 00 00 valid 0 1 0 valid 0 0 valid 0 0 valid 0 0 valid rl rl notes:1. read with bc4 either by mrs or otf 2. memory control must drive 0 on a[1:0] 3. a[2] = 0 selects lower 4 nibble bits 0 ... 3 4. a[2] = 1 selects upper 4 nibble bits 4 ... 7 ck command ba a[1:0] a[2] a[9:3] a10(ap) a[11] a12(/bc) a[15:13] dqs, /dqs dq tmprr pall mrs nop nop read mrs nop * 1 read nop nop t23 t24 t25 t26 t27 t28 t29 t30 t31 t43 trp tccd tmod * 2 * 3 valid 0 1 valid valid valid valid valid * 2 * 4 vih or vil /ck mpr readout predefined pattern, bc4, lower nibble then upper nibble
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 97 t0 t4 t5 t9 t17 t18 t19 t20 t21 t22 t23 t24 t25 t26 t27 t28 t29 t30 t31 t43 tmod * 1 * 1 * 1 tmrd 3 3 valid 0 valid 0 1 0 1 00 00 valid 0 1 0 valid 0 0 valid 0 0 valid 0 0 valid rl rl notes:1. read with bc4 either by mrs or otf 2. memory control must drive 0 on a[1:0] 3. a[2] = 0 selects lower 4 nibble bits 0 ... 3 4. a[2] = 1 selects upper 4 nibble bits 4 ... 7 ck, /ck command ba a[1:0] a[2] a[9:3] a10, ap a[11] a12(/bc) a[15:13] dqs, /dqs dq tmprr pall mrs nop nop read mrs nop * 1 read nop nop trp tccd tmod * 2 * 4 valid 0 0 valid valid valid valid valid * 2 * 3 vih or vil mpr readout of predefined pattern, bc4, upper nibble then lower nibble
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 98 operation of the ddr3 sdram read timing definition read timing is shown in the following figure and is applied when the dll is enabled and locked. rising data strobe edge parameters: ? ? ? ? ? : ? ? ? ck /dqs associated dq pins /ck tdqsck tdqsck tqsl tqsh tqh tdqsq tdqsq tqh tdqsck(max.) tdqsck(min.) tdqsck(min.) tdqsck(max.) dqs rising strobe region rising strobe region read timing definition
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 99 ? ? ? ? ? /ck ck dqs, /dqs early strobe trpre trpst tlz(dqs)(min.) tdqsck(min.) tdqsck(min.) tdqsck(min.) dqs, /dqs late strobe tdqsck(min.) trpre trpst tlz(dqs)(max.) thz(dqs)(max.) bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 rl measured to this point tdqsck(max.) tdqsck(max.) tdqsck(max.) tdqsck(max.) tqsh tqsl tqsh tqsl notes: 1. within a burst, rising strobe edge is not necessarily fixed to be always at tdqsck (min.) or tdqsck (max.). instead, rising strobe edge can vary between tdqsck (min.) and tdqsck (max.). 2. notwithstanding note 1, a rising strobe edge with tdqsck (max) at t (n) can not be immediately followed by a ri sing strobe edge with tdqsck (min.) at t (n+1). this is because other timing relationships (tqsh, tqsl) exist: if tdqsck(n+1) < 0: tdqsck(n) < 1.0 tck - (tqshmin + tqslmin) - | tdqsck (n+1) | 3. the dqs, /dqs differential output high time is defined by tqsh and the dqs, /dqs differential output low time i s defined by tqsl. 4. likewise, tlz (dqs)min and thz (dqs)min are not tied to tdqsckmin (early strobe case) and tlz (dqs) max and thz (dqs) max are not tied to tdqsckmax (late strobe case). 5. the minimum pulse width of read preamble is defined by trpre (min). 6. the maximum read postamble is bound by tdqsck(min.) plus tqsh (min.) on the left side and thz(dqs)(max.) on the right side. 7. the minimum pulse width of read postamble is defined by trpst (min.). 8. the maximum read preamble is bound by tlz (dqs)(min.) on the left side and tdqsck (max.) on the right side. ddr3 clock to data strobe relationship
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 100 ? ? notes: 1. bl8, rl = 5(al = 0, cl = 5). 2. dout n = data-out from column n. 3. nop commands are shown for ease of illustration; other commands may be valid at these times. 4. bl8 setting activated by mr0 bit [a1, a0] = [0, 0] and a12 = 1 during read command at t0. 5. output timings are referenced to vddq/2, and dll on for locking. 6. tdqsq defines the skew between dqs, /dqs to data and does not define dqs, /dqs to clock. 7. early data transitions may not always happen at the same dq. data transitions of a dq can vary(either early or late) within a busy. vih or vil read ck /ck t0 t5 t7 t9 t10 t4 t6 t8 command* 3 dqs, /dqs dq* 2 (last data valid) nop address* 4 bank coln dq* 2 (first data no longer valid) all dqs collectively trpst rl = al + cl tqh tqh trpre tdqsq(max.) dout n dout n+1 dout n+2 dout n+3 dout n+4 dout n+5 dout n+6 dout n+7 data valid data valid dout n dout n+1 dout n+2 dout n+3 dout n+4 dout n+5 dout n+6 dout n+7 dout n dout n+1 dout n+2 dout n+3 dout n+4 dout n+5 dout n+6 dout n+7 tlz(dq)(min.) tlz(dq)(max.) thz(dq)(max.) tdqsq(max.) ddr3 data strobe to data relationship
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 101 tlz (dqs), tlz (dq), thz (dqs), thz (dq) notes thz and tlz transitions occur in the same access time as valid data transitions. these parameters are referenced to a specific voltage level whic h specifies when the device output is no lo nger driving thz(dqs) and thz(dq), or begins driving tlz(dqs), tlz(dq). the figure below shows a method to calculate the point when device is no longer driving thz(dqs) and thz(dq), or begins driving tlz(dqs), tlz(dq) by measuring the signal at two different voltages. the actual voltage measurement points are not critical as long as the calculation is consistent. the parameters tlz(dqs), tlz(dq), thz(dqs), and thz( dq) are defined as singled ended. voh ? x mv voh ? 2x mv vol + 2x mv vol + x mv thz(dqs), thz(dq) thz(dqs), thz(dq) end point = 2 t1 - t2 t1 t2 tlz(dqs), tlz(dq) tlz(dqs), tlz(dq) begin point = 2 t1 - t2 tlz(dqs): ck-/ck rising crossing at rl ? 1 tlz(dq): ck-/ck rising crossing at rl vtt + 2x mv vtt + x mv vtt ? x mv vtt ? 2x mv t2 t1 ck /ck tlz thz(dqs), thz(dq) with bl8: ck-/ck rising crossing at rl + 4nck thz(dqs), thz(dq) with bl4: ck-/ck rising crossing at rl + 2nck ck /ck thz method for calculating transitions and endpoints trpre calculation the method for calculating differential pulse widths for trpre is shown as follows. ck dqs single ended signal, provided as background information single ended signal, provided as background information resulting differential signal, relevant for trpre specification ta tc tb td /dqs dqs - /dqs t1 trpre_begin t2 trpre_end trpre /ck vtt vtt vtt 0v method for calculating trpre transitions and endpoint
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 102 trpst calculation the method for calculating differential pulse widths for trpst is shown as follows. ck dqs single ended signal, provided as background information single ended signal, provided as background information resulting differential signal, relevant for trpst specification ta tc tb td /dqs dqs - /dqs t1 trpst_begin t2 trpst_end trpst /ck vtt vtt vtt 0v method for calculating trpst transitions and endpoint
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 103 read operation during read or write command ddr3 will support bc4 and bl8 on the fly using address a12 during the read or write (auto precharge can be enabled or disabled). ? = = = ? = read /ck ck t0 t2 t4 t6 t8 t10 t1 t3 t5 t7 t9 t11 command* 3 dqs, /dqs dq* 2 nop cl = 5 address* 4 bank col n dout n dout n+1 dout n+2 dout n+3 dout n+4 dout n+5 dout n+6 dout n+7 trpre trpst rl = al + cl notes: 1. bl8, al = 0, rl = 5, cl = 5 2. dout n = data-out from column n. 3. nop commands are shown for ease of illustration; other commands may be valid at these times. 4. bl8 setting activated by mr0 bit [a1, a0] = [0, 0] or mr0 bit [a1, a0] = [0, 1] and a12 = 1 during read comman d at t0. vih or vil burst read operation, rl = 5
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 104 read /ck ck t0 t2 t4 t6 t8 t10 t1 t3 t5 t7 t9 t11 t12 t13 command* 3 dqs, /dqs* 2 dq nop al = 4 trpre rl = al + cl dout n dout n+1 dout n+2 dout n+3 dout n+4 dout n+5 dout n+6 dout n+7 cl = 5 trpst bank col n notes: 1. bl8, rl = 9, al = (cl ? 1), cl = 5 2. dout n = data-out from column n. 3. nop commands are shown for ease of illustration; other commands may be valid at these times. 4. bl8 setting activated by either mr0 bit [a1, a0] = [0, 0] or mr0 bit [a1, a0] = [0, 1] and a12 = 1 during read command at t0. vih or vil address* 4 burst read operation, rl = 9 read read nop /ck ck t0 t4 t3 t6 t8 t10 t12 t5 t7 t9 t11 t13 t14 command* 3 dqs, /dqs dq* 2 rl = 5 tccd trpre rl = 5 dout n+2 dout n+3 dout n+4 dout n+5 dout n+6 dout n+7 dout n dout n+1 dout b+2 dout b+3 dout b+4 dout b+5 dout b+6 dout b+7 dout b dout b+1 trpst notes: 1. bl8, rl = 5 (cl = 5, al = 0). 2. dout n (or b) = data-out from column n (or column b). 3. nop commands are shown for ease of illustration; other commands may be valid at these times. 4. bl8 setting activated by mr0 bit [a1, a0] = [0, 0] or mr0 bit [a1, a0] = [0, 1] and a12 = 1 during read command at t0 and t4. vih or vil address* 4 nop bank col n bank col b read (bl8) to read (bl8)
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 105 read nop /ck ck t0 t4 t3 t6 t8 t10 t12 t5 t7 t9 t11 t13 t14 command* 3 dqs, /dqs dq* 2 rl = 5 tccd = 5 trpre rl = 5 dout n+2 dout n+3 dout n+4 dout n+5 dout n+6 dout n+7 dout n dout n+1 dout b+2 dout b+3 dout b+4 dout b+5 dout b+6 dout b+7 dout b dout b+1 notes: 1. bl8, rl = 5 (cl = 5, al = 0), tccd = 5. 2. dout n (or b) = data-out from column n (or column b). 3. nop commands are shown for ease of illustration; other commands may be valid at these times. 4. bl8 setting activated by mr0 bit [a1, a0] = [0, 0] or mr0 bit [a1, a0] = [0, 1] and a12 = 1 during read command at t0 and t4. 5. dqs-/dqs is held logic low at t9. vih or vil address* 4 nop bank col n bank col b read trpst nop nonconsecutive read (bl8) to read (bl8), tccd = 5 read read nop /ck ck t0 t4 t6 t8 t10 t12 t5 t7 t9 t11 t13 t14 command* 3 dqs, /dqs dq* 2 rl = 5 tccd trpre trpre rl = 5 dout n+2 dout n+3 dout n dout n+1 dout b+2 dout b+3 dout b dout b+1 trpst bank col n bank col b notes: 1. bc4, rl = 5 (cl = 5, al = 0). 2. dout n (or b) = data-out from column n (or column b). 3. nop commands are shown for ease of illustration; other commands may be valid at these times. 4. bc4 setting activated by mr0 bit [a1, a0] = [1, 0] or mr0 bit [a1, a0] = [0, 1] and a12 = 0 during read command at t0 and t4. vih or vil trpst address* 4 nop read (bc4) to read (bc4)
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 106 read writ nop /ck ck t0 t4 t3 t6 t8 t10 t12 t5 t7 t9 t11 t13 t14 t15 command* 3 dqs, /dqs rl = 5 read to writ command delay = rl + tccd + 2tck ? wl trpre twpre wl = 5 tbl = 4 clocks twr bank col n bank col b notes: 1. bl8, rl = 5 (cl = 5, al = 0), wl = 5 (cwl = 5, al = 0). 2. dout n = data-out from column n, din b= data-in from column b. 3. nop commands are shown for ease of illustration; other commands may be valid at these times. 4. bl8 setting activated by mr0 bit [a1, a0] = [0, 0] or mr0 bit [a1, a0] = [0, 1] and a12 = 1 during read command at t0 and writ command t6. vih or vil address* 4 nop twtr dq* 2 trpst dout n+2 dout n+3 dout n+4 dout n+5 dout n+6 dout n+7 dout n dout n+1 din b+2 din b+3 din b+4 din b+5 din b+6 din b+7 din b+1 din b twpst read (bl8) to write (bl8) read writ nop /ck ck t0 t4 t3 t6 t8 t10 t12 t5 t7 t9 t11 t13 t14 t15 command* 3 dqs, /dqs rl = 5 read to writ command delay = rl + tccd/2 + 2tck ? wl trpre twpre wl = 5 tbl = 4 clocks bank col n bank col b notes: 1. bc4, rl = 5 (cl = 5, al = 0), wl = 5 (cwl = 5, al = 0). 2. dout n = data-out from column n, din b= data-in from column b. 3. nop commands are shown for ease of illustration; other commands may be valid at these times. 4. bc4 setting activated by mr0 bit [a1, a0] = [0, 1] and a12 = 0 during read command at t0 and writ command t4. vih or vil address* 4 nop dq* 2 trpst dout n+2 dout n+3 dout n dout n+1 din b+2 din b+3 din b+1 din b twpst twr twtr read (bc4) to write (bc4) otf
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 107 read read nop /ck ck t0 t4 t6 t8 t10 t12 t5 t7 t9 t11 t13 t14 command* 3 dqs, /dqs dq* 2 rl = 5 tccd trpre rl = 5 dout n+2 dout n+3 dout n+4 dout n+5 dout n+6 dout n+7 dout n dout n+1 dout b+2 dout b+3 dout b dout b+1 notes: 1. rl = 5 (cl = 5, al = 0). 2. dout n (or b) = data-out from column n (or column b). 3. nop commands are shown for ease of illustration; other commands may be valid at these times. 4. bc4 setting activated by mr0 bit [a1, a0] = [0, 1] and a12 = 0 during read command at t4. bl8 setting activated by mr0 bit [a1, a0] = [0, 1] and a12 = 1 during read command at t0. vih or vil address* 4 nop bank col n bank col b trpst read (bl8) to read (bc4) otf read read nop ck /ck t0 t4 t6 t8 t10 t12 t5 t7 t9 t11 t13 t14 command* 3 dqs, /dqs dq* 2 rl = 5 tccd trpre trpre rl = 5 dout n+2 dout n+3 dout n dout n+1 dout b+2 dout b+3 dout b dout b+1 dout b+4 dout b+5 dout b+6 dout b+7 notes: 1. rl = 5 (cl = 5, al = 0). 2. dout n (or b) = data-out from column n (or column b). 3. nop commands are shown for ease of illustration; other commands may be valid at these times. 4. bc4 setting activated by mr0 bit [a1, a0] = [0, 1] and a12 = 0 during read command at t0. bl8 setting activated by mr0 bit [a1, a0] = [0, 1] and a12 = 1 during read command at t4. vih or vil address* 4 nop trpst trpst bank col n bank col b read (bc4) read (bl8) otf
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 108 read writ nop /ck ck t0 t4 t3 t6 t8 t10 t12 t5 t7 t9 t11 t13 t14 t15 command* 3 dqs, /dqs rl = 5 trpre twpre wl = 5 tbl = 4 clocks bank col n bank col b notes: 1. rl = 5 (cl = 5, al = 0), wl = 5 (cwl = 5, al = 0). 2. dout n = data-out from column n , din b= data-in from column b. 3. nop commands are shown for ease of illustration; other commands may be valid at these times. 4. bc4 setting activated by mr0 bit [a1, a0] = [0, 1] and a12 = 0 during read command at t0. bl8 setting activated by mr0 bit [a1, a0] = [0, 1] and a12 = 1 during writ command at t4. vih or vil address* 4 nop dq* 2 trpst dout n+2 dout n+3 dout n dout n+1 din b+2 din b+3 din b+1 din b din b+6 din b+7 din b+5 din b+4 twpst read to writ command delay = rl + tccd/2 + 2tck ? wl twr twtr read (bc4) to write (bl8) otf read writ nop /ck ck t0 t4 t3 t6 t8 t10 t12 t5 t7 t9 t11 t13 t14 t15 command* 3 dqs, /dqs rl = 5 read to writ command delay = rl + tccd + 2tck ? wl trpre twpre wl = 5 bank col n bank col b notes: 1. rl = 5 (cl = 5, al = 0), wl = 5 (cwl = 5, al = 0). 2. dout n = data-out from column n, n din b= data-in from column b. 3. nop commands are shown for ease of illustration; other commands may be valid at these times. 4. bl8 setting activated by mr0 bit [a1, a0] = [0, 1] and a12 = 1 during read command at t0. bc4 setting activated by mr0 bit [a1, a0] = [0, 1] and a12 = 0 during writ command at t6. vih or vil address* 4 nop dq* 2 trpst dout n+2 dout n+3 dout n+4 dout n+5 dout n+6 dout n+7 dout n dout n+1 din b+2 din b+3 din b+1 din b twpst tbl = 4 clocks twr twtr read (bl8) to write (bc4) otf
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 109 read pre /ck ck t0 t2 t4 t6 t8 t10 t1 t3 t5 t7 t9 t11 command* 3 dqs, /dqs dq* 2 nop nop cl = 5 address* 4 bank col n dout n dout n+1 dout n+2 dout n+3 dout n+4 dout n+5 dout n+6 dout n+7 trpre trpst rl = al + cl notes: 1. bl8, al = 0, rl = 5, cl = 5 2. dout n = data-out from column n. 3. nop commands are shown for ease of illustration; other commands may be valid at these times. 4. bl8 setting activated by mr0 bit [a1, a0] = [0, 0] or mr0 bit [a1, a0] = [0, 1] and a12 = 1 during read comman d at t0. vih or vil trtp = 4 nck trp burst read precharge operation, rl = 5 read /ck ck t0 t2 t4 t6 t8 t10 t1 t3 t5 t7 t9 t11 t12 t13 command* 3 dqs, /dqs* 2 dq nop al = 4 trpre rl = al + cl dout n dout n+1 dout n+2 dout n+3 dout n+4 dout n+5 dout n+6 dout n+7 cl = 5 trpst bank col n notes: 1. bl8, rl = 9, al = (cl 1), cl = 5 2. dout n = data-out from column n. 3. nop commands are shown for ease of illustration; other commands may be valid at these times. 4. bl8 setting activated by either mr0 bit [a1, a0] = [0, 0] or mr0 bit [a1, a0] = [0, 1] and a12 = 1 during read command at t0. vih or vil address* 4 pre nop trtp = 4 nck internal read command starls here trp burst read precharge operation, rl = 9
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 110 write timing definition t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 wl = al + cwl tdqss(min) tdqss(max) twpre (min) t10 tdqss tdsh tdsh tdsh tdsh tdqsh (min) tdqsh tdqsl tdqsh tdqsl tdss tdss tdss tdss tdss nop writ nop nop nop nop nop nop nop nop nop twpst (min) notes: bl8, wl = 5 (al = 0, cwl = 5) 1. din n = data-in from column n. 2. 3. nop commands are shown for ease of illustration; other commands may be valid at these times. bl8 setting activated by mr0 bit [a1, a0] = [0, 0] or mr0 bit [a1, a0] = [0, 1] and a12 = 1 during writ command at t0. 4. tdqss must be met at each rising clock edge. 5. vih or vil command * 3 dq * 2 dqs, /dqs address* 4 din n din n + 1 din n + 2 din n + 3 din n + 4 din n + 5 din n + 6 din n + 7 bank, col n tdqsh tdqsl tdqsh tdqsl (min) tdqsl twpre (min) tdsh tdsh tdsh tdsh tdqsh (min) tdqsh tdqsl tdqsh tdqsl tdss tdss tdss tdss tdss twpst (min) dq * 2 dqs, /dqs din n din n + 1 din n + 2 din n + 3 din n + 4 din n + 5 din n + 6 din n + 7 tdqsh tdqsl tdqsh tdqsl (min) tdqsl twpre (min) tdqss tdsh tdsh tdsh tdsh tdqsh (min) tdqsh tdqsl tdqsh tdqsl tdss tdss tdss tdss tdss twpst (min) dq * 2 dqs, /dqs din n din n + 1 din n + 2 din n + 3 din n + 4 din n + 5 din n + 6 din n + 7 tdqsh tdqsl tdqsh tdqsl (min) tdqsl 1 ck /ck * write timing definition
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 111 twpre calculation the method for calculating differential pulse widths for twpre is shown as follows. ck resulting differential signal, relevant for twpre specification dqs - /dqs t1 twpre_begin t2 twpre_end twpre /ck vtt 0v method for calculating twpre transitions and endpoints twpst calculation the method for calculating differential pulse widths for twpst is shown as follows. ck resulting differential signal, relevant for twpst specification dqs - /dqs t1 twpst_begin t2 twpst_end twpst /ck vtt 0v method for calculating twpst transitions and endpoints
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 112 write operation during read or write command ddr3 will support bc4 and bl8 on the fly using address a12 during the read or write (auto precharge can be enabled or disabled). ? = = = ? = + writ /ck ck t0 t2 t4 t6 t8 t10 t1 t3 t5 t7 t9 t11 t12 t13 command* 3 dq* 2 nop twpre wl = al + cwl bank col n notes: 1. bl8, wl = 5 (al = 0, cwl = 5) 2. din n = data-in from column n. 3. nop commands are shown for ease of illustration; other commands may be valid at these times. 4. bl8 setting activated by either mr0 bit [a1, a0] = [0, 0] or mr0 bit [a1, a0] = [0, 1] and a12 = 1 during writ command at t0. vih or vil address* 4 dqs, /dqs twpst din n din n+1 din n+2 din n+3 din n+4 din n+5 din n+6 din n+7 burst write operation, wl = 5
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 113 writ /ck ck t0 t2 t4 t6 t8 t10 t1 t3 t5 t7 t9 t11 t12 t13 command* 3 dq* 2 nop al = 4 twpre wl = al + cwl cwl = 5 twpst bank col n notes: 1. bl8, wl = 9 (al = (cl ? 1), cl = 5, cwl = 5) 2. din n = data-in from column n. 3. nop commands are shown for ease of illustration; other commands may be valid at these times. 4. bl8 setting activated by mr0 bit [a1, a0] = [0, 0] or mr0 bit [a1, a0] = [0, 1] and a12 = 1 during writcommand at t0. vih or vil address* 4 din n din n+1 din n+2 din n+3 din n+4 din n+5 din n+6 din n+7 dqs, /dqs burst write operation, wl = 9 writ read /ck ck t0 t2 t4 t6 t8 t10 t1 t3 t5 t7 t9 tn tn+1 tn+2 command* 3 dq* 2 nop twpre bank col n bank col b vih or vil address* 4 dqs, /dqs din n din n+1 din n+2 din n+3 twtr* 5 twpst wl = 5 rl = 5 notes: 1. bc4, wl = 5, rl = 5. 2. din n = data-in from column n; dout b = data-out from column b. 3. nop commands are shown for ease of illustration; other commands may be valid at these times. 4. bc4 setting activated by mr0 bit [a1, a0] = [1, 0] during writ command at t0 and read command at tn. 5. twtr controls the write to read delay to the same device and starts with the first rising clock edge after the last write data shown at t7. write (bc4) to read (bc4) operation
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 114 writ pre /ck ck t0 t2 t4 t6 t8 t10 t1 t3 t5 t7 t9 tn tn+1 tn+2 command* 3 dq* 2 nop twpre bank col n vih or vil address* 4 dqs, /dqs din n din n+1 din n+2 din n+3 twr* 5 twpst wl = 5 notes: 1. bc4, wl = 5, rl = 5. 2. din n = data-in from column n. 3. nop commands are shown for ease of illustration; other commands may be valid at these times. 4. bc4 setting activated by mr0 bit [a1, a0] = [1, 0] during writ command at t0. 5. the write recovery time (twr) referenced from the first rising clock edge after the last write data shown at t7. twr specifies the last burst write cycle until the precharge command can be issued to the same bank . write (bc4) to precharge operation writ writ nop /ck ck t0 t2 t4 t6 t8 t10 t1 t3 t5 t7 t9 t11 t12 t13 command* 3 dq* 2 nop twpre bank col n bank col b vih or vil address* 4 dqs, /dqs din b din b+1 din n+6 din n+7 din b+2 din b+3 din b+4 din b+5 din b+6 din b+7 tccd twpst wl = 5 wl = 5 notes: 1. bl8, wl = 5 (cwl = 5, al = 0) 2. din n (or b) = data-in from column n (or column b). 3. nop commands are shown for ease of illustration; other commands may be valid at these times. 4. bl8 setting activated by either mr0 bit [a1, a0] = [0, 0] or mr0 bit [a1, a0] = [0, 1] and a12 = 1 during writ c ommand at t0 and t4. din n+2 din n+3 din n din n+1 din n+4 din n+5 twr twtr tbl = 4 clocks write (bl8) to write (bl8) otf
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 115 writ writ /ck ck t0 t2 t4 t6 t8 t10 t1 t3 t5 t7 t9 t11 t12 t13 command* 3 dq* 2 nop nop twpre bank col n bank col b vih or vil address* 4 dqs, /dqs din b din b+1 din b+2 din b+3 tccd twpre twpst twpst wl = 5 wl = 5 notes: 1. bc4, wl = 5 (cwl = 5, al = 0) 2. din n (or b) = data-in from column n (or column b). 3. nop commands are shown for ease of illustration; other commands may be valid at these times. 4. bc4 setting activated by either mr0 bit [a1, a0] = [0, 1] and a12 = 0 during writ command at t0 and t4. din n+2 din n+3 din n din n+1 twr twtr tbl = 4 clocks write (bc4) to write (bc4) otf writ read /ck ck t0 t2 t4 t6 t8 t10 t1 t3 t5 t7 t9 t11 t12 t13 t14 command* 3 dq* 2 nop nop twpre bank col n bank col b vih or vil address* 4 dqs, /dqs din n+6 din n+7 twpst wl = 5 rl = 5 notes: 1. rl = 5 (cl = 5, al = 0), wl = 5 (cwl = 5, al = 0) 2. din n = data-in from column n; dout b = data-out from column b. 3. nop commands are shown for ease of illustration; other commands may be valid at these times. 4. bl8 setting activated by mr0 bit [a1, a0] = [0, 0] or mr0 bit [a1, a0] = [0, 1] and a12 = 1 during writ comma nd at t0. read command at t13 can be either bc4 or bl8 depending on mr0 bit [a1, a0] and a12 status at t13. din n+2 din n+3 din n din n+1 din n+4 din n+5 twtr write (bl8) to read (bc4/bl8) otf
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 116 writ read /ck ck t0 t2 t4 t6 t8 t10 t1 t3 t5 t7 t9 t11 t12 t13 t14 command* 3 dq* 2 nop nop twpre bank col n bank col b vih or vil address* 4 dqs, /dqs tbl = 4 clocks twpst wl = 5 notes: 1. bc4, rl = 5 (cl = 5, al = 0), wl = 5 (cwl = 5, al = 0) 2. din n = data-in from column n; dout b = data-out from column b. 3. nop commands are shown for ease of illustration; other commands may be valid at these times. 4. bc4 setting activated by mr0 bit [a1, a0] = [0, 1] and a12 = 0 during writ command at t0. read command at t13 can be either bc4 or bl8 depending on mr0 bit [a1, a0] and a12 status at t13. din n+2 din n+3 din n din n+1 twtr rl = 5 write (bc4) to read (bc4/bl8) otf writ writ /ck ck t0 t2 t4 t6 t8 t10 t1 t3 t5 t7 t9 t11 t12 t13 t14 command* 3 dq* 2 nop nop twpre bank col n bank col b vih or vil address* 4 dqs, /dqs din b din b+1 din n+6 din n+7 din b+2 din b+3 tccd twpst wl = 5 notes: 1. wl = 5 (cwl = 5, al = 0) 2. din n (or b) = data-in from column n (or column b). 3. nop commands are shown for ease of illustration; other commands may be valid at these times. 4. bl8 setting activated by mr0 bit [a1, a0] = [0, 1] and a12 = 1 during writ command at t0. bc4 setting activated by mr0 bit [a1, a0] = [0, 1] and a12 = 0 during writ command at t4. din n+2 din n+3 din n din n+1 din n+4 din n+5 twr twtr tbl = 4 clocks wl = 5 write (bl8) to write (bc4) otf
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 117 writ writ /ck ck t0 t2 t4 t6 t8 t10 t1 t3 t5 t7 t9 t11 t12 t13 t14 command* 3 dq* 2 nop nop twpre bank col n bank col b vih or vil address* 4 dqs, /dqs din b din b+1 din b+2 din b+3 din b+4 din b+5 din b+6 din b+7 tccd twpre twpst twpst wl = 5 notes: 1. wl = 5 (cwl = 5, al = 0) 2. din n (or b) = data-in from column n (or column b). 3. nop commands are shown for ease of illustration; other commands may be valid at these times. 4. bc4 setting activated by mr0 bit [a1, a0] = [0, 1] and a12 = 0 during writ command at t0. bl8 setting activated by mr0 bit [a1, a0] = [0, 1] and a12 = 1 during writ command at t4. din n+2 din n+3 din n din n+1 twr twtr tbl = 4 clocks wl = 5 write (bc4) to write (bl8) otf
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 118 write timing violations motivation generally, if timing parameters are violated, a complete rese t/initialization procedure has to be initiated to make sure the dram works properly. however it is desirable for certain minor violations, that the dram is guaranteed not to "hang up" and error to be limited to that part icular operation. for the following it will be assumed that there are no timing violations w.r.t to the write command itself (including odt etc.) and that it does satisfy all ti ming requirements not mentioned below. data setup and hold violations should the data to strobe timing requirements (tds, tdh) be violated, for any of the st robe edges associated with a write burst, then wrong data might be written to the me mory location addressed with this write command. in the example (figure write timing parameters) the releva nt strobe edges for write burst a are associated with the clock edges: t5, t5.5, t6, t6.5, t7, t7.5, t8, t8.5. subsequent reads from that location might result in unpredictable read data, however the dram will work properly otherwise. strobe to strobe and strobe to clock violations should the strobe timing requirements (tdqsh, tdqsl, twpre, twpst) or t he strobe to clock timing requirements (tdss, tdsh tdqss) be violated for any of the strobe edges associated with a write burst, then wrong data might be written to the memory location addressed with the offendi ng write command. subsequent reads from that location might result in unpredictable read data, however the dram will work properly otherwise. in the example (figure write (bl8) to write (bl8) otf) the rele vant strobe edges for write burst n are associated with the clock edges: t4, t4.5, t5, t5.5, t6, t6.5, t7, t7.5, t8, t8.5 and t9. any timing requirements starting and ending on one of these strobe edges are t8, t8.5, t9, t9.5, t10, t10.5, t11, t11.5, t12, t12.5 and t13. some edges are associated with both bursts. writ writ nop /ck ck t0 t4 t3 t6 t8 t10 t12 t5 t7 t9 t11 t13 t14 command* 3 dqs, /dqs dq* 2 odtl wl bl/2 + 2 + odtl twpre twpst vih or vil tdqsl tdqsh tdsh address* 4 /cs nop tdss tdqss a b tdh tds write timing parameters
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 119 write data mask one write data mask (dm) pin for each 8 data bits (dq) wi ll be supported on ddr3 sdrams, consistent with the implementation on ddr-i sdrams. it has identical timings on wr ite operations as the data bits, and though used in a uni-directional manner, is internally loaded identically to data bits to ensure matched system timing. dm is not used during read cycles. dq dqs /dqs t1 t2 t3 t4 t5 t6 dm write mask latency = 0 in in in in in in in in data mask timing /ck ck dqs, /dqs dq dm dqs, /dqs dq dm command [tdqss(min.)] twr tdqss wl tdqss wl [tdqss(max.)] writ nop in0 in2 in3 in0 in2 in3 data mask function, wl = 5, al = 0 shown
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 120 precharge the precharge command is used to prec harge or close a bank that has been ac tivated. the precharge command is triggered when /cs, /ras and /we are low and /cas is hi gh at the rising edge of the clock. the precharge command can be used to precharge each bank independently or all banks simultaneously. four address bits a10, ba0, ba1 and ba2 are used to define which bank to precharge when the command is issued. [bank selection for precharge by address bits] a10 ba0 ba1 ba2 precharged bank(s) l l l l bank 0 only l h l l bank 1 only l l h l bank 2 only l h h l bank 3 only l l l h bank 4 only l h l h bank 5 only l l h h bank 6 only l h h h bank 7 only h : : : :
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 121 auto precharge operation before a new row in an active bank can be opened, the ac tive bank must be precharged using either the precharge command or the auto precharge function. when a read or a write command is given to the ddr3 sdram, the /cas timing accepts one extra address, column address a10, to a llow the active bank to automat ically begin precharge at the earliest possible moment during the bu rst read or write cycle. if a10 is low when the read or write command is issued, then normal read or write burst operation is execut ed and the bank remains active at the completion of the burst sequence. if a10 is high when the read or write command is issued, then the auto precharge function is engaged. during auto precharge, a read command will execut e as normal with the exception that the active bank will begin to precharge on the rising edge which is /cas late ncy (cl) clock cycles before the end of the read burst. auto precharge can also be implemented during write commands. the precharge operation engaged by the auto precharge command will not begin until the la st data of the burst wr ite sequence is properly stored in the memory array. this feature allows the prec harge operation to be partially or completely hidden during burst read cycles (dependent upon /cas latency) thus improving system performance for random data access. the /ras lockout circuit internally delays the precharge operation until the array restore ope ration has been completed so that the auto precharge command may be issued with any read or write command. burst read with auto precharge if a10 is high when a read command is issued, the read with auto precharge function is engaged. the ddr3 sdram starts an auto precharge operation on the rising edge which is (al + trtp) cycles later from the read with ap command when tras (min.) is satisfied. if tras (min.) is not satisfied at the ed ge, the start point of auto precharge operation will be delayed until tras (min.) is sati sfied. a new bank active (command) may be issued to the same bank if the following two conditions are satisfied simultaneously. (1) the /ras precharge time (trp) has been satisfied from the clock at which the auto precharge begins. (2) the /ras cycle time (trc) from the prev ious bank activation has been satisfied. burst write with auto precharge if a10 is high when a write command is issued, the writ e with auto precharge function is engaged. the ddr3 sdram automatically begins precharge operation after the co mpletion of the burst writes plus write recovery time (twr). the bank-undergoing auto precha rge from the completion of the writ e burst may be reactivated if the following two conditions are satisfied. (1) the data-in to bank activate delay time (twr + trp) has been satisfied. (2) the /ras cycle time (trc) from the prev ious bank activation has been satisfied.
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 122 auto-refresh the refresh command (ref) is used during normal opera tion of the ddr3 sdrams. this command is non persistent, so it must be issued each time a refresh is required. the ddr3 sdram requires refresh cycles at an average periodic interval of trefi. when /cs, /ras and /cas are held low and /we high at the rising edge of the clock, the chip enters a refresh cycle. all banks of t he sdram must be precharged and idle for a minimum of the precharge time trp(min) before the refresh command can be applied. the refresh addressing is generated by the internal refresh controller. this makes the address bits ?don?t care? during a refresh command. an internal address counter supplies the addresses during the refresh cycle. no control of the ex ternal address bus is required once this cycle has started. when the refresh cycle has completed, all banks of the sdram will be in the precharged (idle) state. a delay between the refresh command and the nex t valid command, except nop or desl, must be greater than or equal to the minimum refresh cycle time trfc(min) as shown in the following figure. note that the trfc timing parameter depends on memory density. in general, a refresh command needs to be issued to the ddr3 sdram regularly every trefi interval. to allow for improved efficiency in scheduling and switching between tasks, some flexibility in the absolute refresh interval is provided. a maximum of 8 refresh commands can be postponed during operation of the ddr3 sdram, meaning that at no point in time more than a to tal of 8 refresh commands are allowed to be postponed. in case that 8 refresh commands are postponed in a row, the resulting maximu m interval between the surrounding refresh commands is limited to 9 trefi. a maximum of 8 additional refresh co mmands can be issued in advance (?pulled in?), with each one reducing the number of regular refresh commands requir ed later by one. note that pulling in more than 8 refresh commands in advance does not further reduce the number of regular refresh commands required later, so that the resulting maximum interval between two surrounding refresh commands is limited to 9 trefi. at any given time, a maximum of 16 ref commands can be issued within 2 trefi. self-refresh mode may be entered with a maximum of eight refresh commands being postponed. afte r exiting self-refresh mode with one or more refresh commands postponed, additional refresh commands may be pos tponed to the extent t hat the total number of postponed refresh commands (before and after the self-refr esh) will never exceed eight. during self-refresh mode, the number of postponed or pulled- in ref commands does not change. nop pre ck /ck t0 t1 t2 t3 cke command trp vih trfc trfc ref ref nop any command refresh command timing trefi trfc t 9 trefi 8 ref-commands postponed postponing refresh command trefi trfc t 9 trefi 8 ref-commands pulled-in pulling-in refresh command
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 123 self-refresh the self-refresh command can be used to retain data in the ddr3 sdram, even if the rest of the system is powered down. when in the self-refresh mode, the ddr3 sdram re tains data without external clocking. the ddr3 sdram device has a built-in timer to accommodate self-refresh operation. the self-refres h entry (self) command is defined by having /cs, /ras, /cas and cke held low wi th /we high at the rising edge of the clock. before issuing the self-refresh entry command, the ddr3 s dram must be idle with all bank precharge state with trp satisfied. ?idle state? is defined as all banks are closed (trp, tdal, etc. sa tisfied), no data bursts are in progress, cke is high, and all timings from pr evious operations are satisfied (tmrd, tmod, trfc, tzqinit, tzqoper, tzqcs, etc.) also, on-die termination must be turned off before issu ing self-refresh entry command, by either registering odt pin low ?odtl + 0.5tck? prior to the self-refresh entry command or using mrs to mr1 command. once the self-refresh entry command is registered, cke must be held low to keep the device in self-refresh mode. during normal operation (dll on), mr1 (a0 = 0), the dll is auto matically disabled upon entering self-refresh and is automatically enabled (including a dl l-reset) upon exiting self-refresh. when the ddr3 sdram has entered self-re fresh mode all of the external cont rol signals, except cke and /reset, are ?don?t care?. for proper self-refr esh operation, all power supply and reference pins (vdd, vddq, vss, vssq, vrefca and vrefdq) must be at valid levels. vrefdq supply may be turned off and vrefdq may take any value between vss and vdd during self-refresh operation, prov ided that vrefdq is valid and stable prior to cke going back high and that first write operation or first writ e leveling activity may not occur earlier than 512 nck after exit from self-refresh. the dram init iates a minimum of one refresh command internally within tckesr period once it enters self-refresh mode. the clock is internally disabled during self-refresh operat ion to save power. the minimum time that the ddr3 sdram must remain in self-refresh mode is tckesr. the user may change the external clock frequency or halt the external clock tcksre cycles after self -refresh entry is registered, however, the clock must be restarted and stable tcksrx clock cycles before the device c an exit self-refresh operation. to pr otect dram internal delay on cke line to block the input signals, one nop (or desl) command is needed after self-refresh entry. the procedure for exiting self-refresh requires a sequence of events. first, the clock must be stable prior to cke going back high. once a self-refresh exit command (sre x, combination of cke going high and either nop or desl on command bus) is registered, a delay of at least txs must be satisfied before a valid command not requiring a locked dll can be issued to the device to allow for any internal refresh in progress. before a command that requires a locked dll can be appl ied, a delay of at least txsdll must be satisfied. depending on the system environment and the amount of time spent in self -refresh, zq calibration commands may be required to compensate for the voltage and temperature dr ift as described in zq calibration section. to issue zq calibration commands, applicable timing requirement s must be satisfied (see figure zq calibration). cke must remain high for the entire se lf-refresh exit period txsdll for proper operation except for self-refresh re-entry. upon exit from self-refresh, the ddr3 sdram can be put back into self-refresh mode after waiting at least txs period and issuing one refresh command (refresh period of trfc). nop or desl commands must be registered on each positive clock edge during the self-refresh exit in terval txs. odt must be turned off during txsdll. the use of self-refresh mode introduces the possibility th at an internally timed refresh event can be missed when cke is raised for exit from self-refresh mode. upon exit from self-refresh, the ddr3 sdram requires a minimum of one extra refresh command before it is put back into self-refresh mode.
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 124 tcksre tckesr txs odtloff + 0.5 x tck trp * 2 * 2 * 3 * 3 notes: 1. only nop or desl commands. 2. valid commands not requiring a locked dll. 3. valid commands requiring a locked dll. 4. one nop or desl commands. ck, /ck odt command self nop pall srex valid * 1 * 4 ta tb tc tc+1tc+2 te td tf tf+1 tf+2 tg+1 tg th+1 th cke tcksrx txsdll valid valid valid self-refresh entry and exit timing
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 125 power-down mode power-down is synchronously entered when cke is register ed low (along with nop or desl command). cke is not allowed to go low while mode register set command, mp r operations, zqcal operations, dll locking or read/write operation are in progress. cke is allowed to go low while an y of other operations such as row activation, precharge or auto precharge and refresh are in progress, but power-down idd spec will not be applied until finishing those operations. the dll should be in a locked state when power-down is enter ed for fastest power-down exit timing. if the dll is not locked during power-down entry, the dll must be reset after exiting power-down mode for proper read operation and synchronous odt operation. dram design provides a ll ac and dc timing and voltage specification as well proper dll operation with any cke intensive operat ions as long as dram controller complies with dram specifications. during power-down, if all banks are closed after any in-progress commands are completed, the device will be in precharge power-down mode; if any bank is open after in -progress commands are completed, the device will be in active power-down mode. entering power-down deactivates the input and output buffers, excluding ck, /ck, odt, cke and /reset. to protect dram internal delay on cke line to block the input signals, multiple nop or desl commands are needed during the cke switch off and cycle(s) after this timing period are defined as tcpded. cke_low will result in deactivation of command and address receivers after tcpded has expired. [power-down entry definitions] status of dram mr0 bit a12 dll pd exit relevant parameters active (a bank or more open) don?t care on fast txp to any valid command precharged (all banks precharged) 0 off slow txp to any valid command. since it is in precharge state, commands here will be act, ar, mrs, pre or pall . txpdll to commands who need dll to operate, such as read, reada or odt control line. precharged (all banks precharged) 1 on fast txp to any valid command also the dll is disabled upon entering precharge power-do wn for slow exit mode, but the dll is kept enabled during precharge power-down for fast exit mode or active power-down. in power-down mode, cke low, reset high and a stable clock signal must be maintained at the input s of the ddr3 sdram, and odt should be in a valid state but all other input signals are ?don?t care? (if reset goe s low during power-down, the dram will be out of pd mode and into reset state). cke low must be maintain ed until tpd has been satisfied. power-down duration is limited by 9 times trefi of the device. the power-down state is synchronously exited when cke is registered high (along with a nop or desl command). cke high must be maintained until tcke has been satisfied. a valid, executable command can be applied with power-down exit latency, txp and/or txpdll after cke goes high. power-down exit latency is defined at ac characteristics table of this data sheet.
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 126 timing diagrams for proposed cke with power-down entry, power-down exit ck command cke dq(bl8) /ck t5 t7 t8 t9 t10 t11 t0 t1 t6 t12 tx tx+1 out 0 out 1 out 2 out 3 vih read ba valid nop dq(bc4) out 0 out 1 out 2 out 3 out 4 out 5 out 6 out 7 trdpden tcpded tpd tis rl = cl + al = 5 (al = 0) nop power-down entry after read and read with auto precharge t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 tn ck ba command cke /ck t10 t14 t15 t16 t17 t18 writa valid nop nop nop tcpded tpd twr * note: twr is programmed through mrs. wl=5 twrapden tis start internal precharge in 0 in 1 in 2 in 3 in 0 in 1 in 2 in 3 in 4 in 5 in 6 in 7 dq(bc4) dq(bl8) power-down entry after write with auto precharge
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 127 t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 ck ba command cke /ck t10 tx tx+1 tx+2 tx+3 write valid nop nop tcpded tpd twr wl=5 twrpden tis in 0 in 1 in 2 in 3 in 0 in 1 in 2 in 3 in 4 in 5 in 6 in 7 dq(bl8) dq(bc4) power-down entry after write t0 t1 tn tn+1 tx ty txp tcpded tcke (min.) tpd ck command cke /ck enter power-down mode note: valid command at t0 is act, nop, desl or precharge with still one bank remaining open after completion of precharge command. exit power-down tih tih tis tis valid nop nop nop nop nop nop nop valid nop nop nop nop n active power-down entry and exit timing diagram t0 t1 tn tn+1 tx ty txp tcpded tcke (min.) tpd ck command cke /ck enter power-down mode exit power-down tih tih tis tis nop nop nop nop nop nop nop valid nop nop nop nop n valid precharge power-down (fast exit mode) entry and exit
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 128 t0 t1 tn tx ty ck command cke /ck tn+1 enter power-down mode exit power-down nop nop nop nop nop nop nop nop valid nop valid nop no txp txpdll tcpded tcke (min.) tpd tih tih tis tis valid precharge power-down (slow exit mode) entry and exit t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 ck command cke /ck nop nop valid tcpded trefpden tis refresh command to power-down entry t0 t1 t2 t3 t4 tn end ck command cke /ck tn+1 tn+2 nop nop valid tcpded tactpden tpd tis active command to power-down entry
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 129 t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 end ck command cke /ck nop nop valid tcpded tprepden tis precharge/precharge all command to power-down entry t0 t1 t2 t3 tn tn+1 tn+2 tn+3 tn+4 tn+5 tn+6 tn+7 ck command cke /ck mrs nop nop nop nop nop tmrspden tcpded tis mrs command to power-down entry
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 130 timing values txxxpden parameters status of dram last command before cke_low parameter parameter value unit idle or active activate tactpden 1 nck idle or active precharge tprpden 1 nck active read/reada trdpden rl + 4 + 1 nck active writ for bl8mrs, bl8otf, bc4o tf twrpden wl + 4 + (twr/tck (avg)) * 1 nck active writ for bc4mrs twrpden wl + 2 + (twr/tck (avg))* 1 nck active writa for bl8mrs, bl8otf, bc4otf twrapden wl + 4 + wr* 2 + 1 nck active writa for bc4mrs twrapden wl + 2 + wr* 2 + 1 nck idle refresh trefpden 1 nck idle mode register set tmrspden tmod notes: 1. twr is defined in ns, for calculation of twrpden, it is necessary to round up twr / tck to next integer. 2. wr in clock cycles as programmed in mode register. power-down entry and exit clarification case 1: when cke registered low for power-down entry, tpd must be satisfied before cke can be registered high for power- down exit. case 1a: after power-down exit, tcke must be satisfied before cke can be registered low again. t0 t1 tn tn+1 tx ty tcpded tcke tpd ck command cke /ck enter power-down exit power-down tih tih tis tis valid nop nop nop nop nop nop nop nop nop nop nop nop n power-down entry/exit clarifications (1)
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 131 case 2: for certain cke intensive operations, for example, repeated "pd exit - refresh - pd entry" sequence, the number of clock cycles between pd exit and pd entry may be insuffi cient to keep the dll updated . therefore the following conditions must be met in addition to tpd in order to maintain proper dram operation when refresh commands is issued in between pd exit and pd entry. power-down mode can be used in conjunction with refresh command if the following conditions are met: 1. txp must be satisfied before issuing the command 2. txpdll must be satisfied (referenced to registra tion of pd exit) before next power-down can be entered. t0 t1 tn tn+1 tx ty tcpded tcke (min.) txpdll (min.) tpd ck command cke /ck enter power-down exit power-down tih tih tis tis txp valid nop nop nop nop nop nop nop nop nop nop ref nop power-down entry/exit clarifications (2) case 3: if an early pd entry is issued after refresh command, once pd exit is issued, nop or desl with cke high must be issued until trfc from the refresh command is satisfied. this means cke cannot be de-asserted twice within trfc window. t0 t1 tn tn+1 tx ty tcpded tcke (min.) trfc (min.) tpd txpdll ck command cke /ck enter power-down note: * synchronous odt timing starts at the end of txpdll (min.) exit power-down tih tih tis tis ref nop nop nop nop nop nop nop nop nop nop nop n nop power-down entry/exit clarifications (3)
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 132 input clock frequency change during precharge power-down once the ddr3 sdram is initialized, the ddr3 sdram requires the clock to be ?s table? during almost all states of normal operation. this means once t he clock frequency has been set and is to be in the ?stable state?, the clock period is not allowed to deviate except for what is allowed for by the clock jitter and ssc (spread spectrum clocking) specifications. the input clock frequency can be changed from one stable clock rate to another stable clock rate under two conditions: (1) self-refresh mode and (2) precharge power-down mode. outside of these two modes, it is illegal to change the clock frequency. for the first condition, once the ddr3 sdram has been successfully placed in to self- refresh mode and tcksre has been satisfied, the state of the clock becomes a don?t care. once a don?t care, changing the clock frequency is permissible, provided t he new clock frequency is stable prior to tcksrx. when entering and exiting self-refresh mode fo r the sole purpose of changing the clo ck frequency, the self-refresh entry and exit specifications must still be met as outlined in self-refresh section. the second condition is when the ddr3 sdram is in prechar ge power-down mode (either fast exit mode or slow exit mode.) odt must be at a logic low ensuring rtt is in an off state prior to entering precharge power-down mode and cke must be at a logic low. a minimum of tcksre mu st occur after cke goes low before the clock frequency may change. the ddr3 sdram input clock frequency is allowed to change only within the minimum and maximum operating frequency specified for the particular speed gra de. during the input clock frequency change, odt and cke must be held at stable low levels. once the inpu t clock frequency is changed, stable new clocks must be provided to the dram tcksrx before precharge power-down may be exited; after precharge power-down is exited and txp has expired, the dll must be reset via mrs. depending on the new clock frequency additional mrs commands may need to be issued to appropriately set the wr, cl, and cwl with cke continuously registered high. during dll relock period, odt must rema in low. after the dll lock time, the dram is ready to operate with new clock frequency. this process is depicted in the fi gure clock frequency change in precharge power-down mode. ck cke t2 tb tc tc+1 td t0 t1 ta /ck td+1 enter precharge power-down mode odt command te te+1 dqs, /dqs nop nop nop nop nop mrs valid exit precharge power-down mode txp high-z high-z frequency change nop address valid tih tis tcksre new clock frequency previous clock frequency tcpded tcksrx dll reset taofpd/taof dq dm tdllk notes: 1. applicable for both slow exit and fast exit precharge power-down. 2. tcksre and tcksrx are self-refresh mode specifications but the values they represent are applicable here. 3. taofpd and taof must be satisfied and outputs high-z prior to t1; refer to odt timing for exact requirements. clock frequency change in precharge power-down mode
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 133 on-die termination (odt) odt (on-die termination) is a featur e of the ddr3 sdram that allows the dram to turn on/off termination resistance for each dq, dqs, /dqs and dm for = to other circuitry like rcv, ... odt vddq/2 rtt switch dq, dqs, dm, tdqs functional representation of odt the switch is enabled by the internal odt control logi c, which uses the external odt pin and other control information, see below. the value of rtt is dete rmined by the settings of mode register bits (see mr1 programming figure in the section progr amming the mode register). the odt pin will be ignored if the mode register mr1 is programmed to disable odt and in self-refresh mode. odt mode register and odt truth table the odt mode is enabled if either of mr1 bits a2 or a6 or a9 are non-zero. in this case the value of rtt is determined by the settings of those bits. application: controller sends writ command together with odt asserted. ? : ? ? ?
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 134 synchronous odt mode synchronous odt mode is selected whenever the dll is turned on and locked. based on the power-down definition, these modes are: ? ? ? ? : = = = + ? = + ? = + = + :
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 135 t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 end ck cke intodt odt rtt /ck odth4 (min.) al = 3 al = 3 odtlon = cwl + al ? 2 odtloff = cwl + al ? 2 cwl ? 2 rtt taof (max.) taof (min.) taon (max.) taon (min.) synchronous odt timing examples (1): al=3, cwl = 5; odtlon = al + cwl - 2 = 6; odtloff = al + cwl - 2 = 6 ck cke command odt dram_rtt /ck t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 odth4 odth4 odth4 odtlon = wl ? 2 odtlon = wl ? 2 odtloff = wl ? 2 odtloff = wl ? 2 wrs4 rtt rtt taon (max.) taon (min.) taof (max.) taof (min.) taof (max.) taof (min.) taon (min.) taon (max.) synchronous odt timing examples (2)*: bc4, wl = 7 odt must be held high for at least odth4 after assertion (t1); odt must be kept high odth4 (bc4) or odth8 (bl8) after write command (t7). odth is measured from od t first registered high to odt first registered low, or from registration of write command with odt high to odt r egistered low. note that although odth4 is satisfied from odt registered high at t6 odt must not go low be fore t11 as odth4 must also be satisfied from the registration of the write command at t7.
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 136 odt during reads as the ddr3 sdram cannot terminate and drive at the same time, rtt must be disabled at least half a clock cycle before the read preamble by driving the odt pin low appropriately. rtt may nominally not be enabled until one clock cycle after the end of the post-amble as shown in the example in the figure below. note that odt may be disabled earlier before the read and enabled later after the read than shown in this example in the figure below. odt must be disabled externally during reads by driving odt low. (example: cl = 6; al = cl - 1 = 5; rl = al + cl = 11; cwl = 5; odtlon = cwl + al -2 = 8; odtloff = cwl + al - 2 = 8) dram_rtt ck command address odt dqs, /dqs dq /ck t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 end rl = al + cl odtloff = wl ? 2 = cwl + al ? 2 odtlon = wl ? 2 = cwl + al ? 2 read a out 0 rtt rtt out 1 out 2 out 3 out 4 out 5 out 6 out 7 taon (min.) taon (max.) taof (max.) taof (min.) example of odt during reads
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 137 dynamic odt in certain application cases and to further enhance signal int egrity on the data bus, it is desirable that the termination strength of the ddr3 sdram c an be changed without issuing an mrs command. this requirement is supported by the ?dynamic odt? feature as described as follows: functional description: the dynamic odt mode is enabled if bit a9 or a10 of mr2 is set to ?1?. the function and is described as follows: ? : ? ? ? : ? ? ? : ? ? ? : = = = = + = + = = =
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 138 mode register settings for dynamic odt mode: the table mode register for rtt selection shows the mode register bits to select rtt_nom and rtt_wr values. [mode register for rtt selection] mr1 mr2 a9 a6 a2 rtt_nom (rzq) rtt_nom ( ? ? : ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? : = ? ck command odt rtt dqs, /dqs dq /ck t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 t18 t19 in 0 wrs4 odtlcnw odtlcwn4 odtlon odtloff odth4 odth4 wl rtt_nom rtt_nom rtt_wr taon (min.) tadc (min.) tadc (min.) taof (min.) tadc (max.) tadc (max.) taon (max.) taof (max.) in 1 in 2 in 3 dynamic odt: behavior with odt being asserted before and after the write* note: example for bc4 (via mrs or otf), al = 0, cwl = 5. odth4 applies to first registering odt high and to the registration of the write command. in this example odth4 would be satisfied if odt is low at t8 (4 clocks after the write command).
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 139 ck command odt rtt dqs, /dqs dq /ck t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 odth4 rtt_nom taon (min.) taon (max.) taof (min.) taof (max.) odtlon odtloff dynamic odt*: behavior without write command; al = 0, cwl = 5 note: odth4 is defined from odt registered high to odt r egistered low, so in this example odth4 is satisfied; odt registered low at t5 would also be legal. ck command odt rtt dqs, /dqs dq /ck t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 rtt_wr taon (min.) tadc (max.) taof (min.) taof (max.) odtlcnw odtlcwn8 odtlon odtloff wrs8 in 0 wl odth8 in 1 in 2 in 3 in 4 in 5 in 6 in 7 dynamic odt*: behavior with odt pin being asserted together with write command for duration of 6 clock cycles note: example for bl8 (via mrs or otf), al = 0, cwl = 5. in this example odth8 = 6 is exactly satisfied.
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 140 ck command odt rtt dqs, /dqs dq /ck t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 t10 t11 rtt_wr rtt_nom taon (min.) tadc (max.) taof (min.) taof (max.) tadc (min.) tadc (max.) odtlcnw odtlcwn4 odtlon odtloff wrs4 in 0 wl odth4 in 1 in 2 in 3 dynamic odt*: behavior with odt pin being asserted together with write command for a duration of 6 clock cycles, example fo r bc4 (via mrs or otf), al = 0, cwl = 5. note: odth4 is defined from odt registered high to odt r egistered low, so in this example odth4 is satisfied; odt registered low at t5 would also be legal. ck command odt rtt dqs, /dqs dq /ck t0 t1 t2 t3 t4 t5 t6 t7 t8 t9 odtlcnw odtlcwn4 odtlon odtloff wrs4 in 0 wl tadc (max.) taof (max.) rtt_wr taon (min.) taof (min.) odth4 in 1 in 2 in 3 dynamic odt*: behavior with odt pin being asserted together with write command for duration of 4 clock cycles note: example for bc4 (via mrs or otf), al = 0, cwl = 5. in this example odth4 = 4 is exactly satisfied.
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 141 asynchronous odt mode asynchronous odt mode is selected when dram runs in dll-on mode, but dll is temporarily disabled (i.e. frozen) in precharge power-down (by mr0 bit a12). precharge power-down mode if dll is disabled during precharge power-down by mr0 bit a12. in asynchronous odt timing mode, internal odt command is not delayed by additive latency (al) relative to the external odt command. in asynchronous odt mode, the following timing param eters apply (see figure asynchronous odt timings): taonpd (min.), (max.), taofpd (min.),(max.) minimum rtt turn-on time (taonpd (min.)) is the point in time when the device termination circuit leaves high impedance state and odt resistance begins to turn on. maxi mum rtt turn-on time (taonpd (max.)) is the point in time when the odt resistance is fully on. taonpd (min.) and taonpd (max.) are measured from odt being sampled high. minimum rtt turn-off time (taofpd (min.)) is the point in time when the devices termination circuit starts to turn off the odt resistance. maximum odt turn-o ff time (taofpd (max.)) is the point in time when the on-die termination has reached high impedance. taofpd (min.) and taofpd (max.) are measured from odt being sampled low. ck odt cke dram_rtt /ck rtt tih tis tih tis taonpd (max.) taonpd (min.) taofpd (max.) taofpd (min.) asynchronous odt timings on ddr3 sdram with fast odt tr ansition: al is ignored in precharge power-down, odt receiver remains active, however no read or write command can be issued, as the respective address/command receivers may be disabled. [asynchronous odt timing parameters for all speed bins] symbol parameters min. max. unit taonpd asynchronous rtt turn-on delay (power-down with dll frozen) 2 8.5 ns taofpd asynchronous rtt turn-off delay (power-down with dll frozen) 2 8.5 ns [odt for power-down (with dll frozen) entry and exit transition period] description min. max. odt to rtt turn-on delay min {odtlon + + ? + ? + + + ? + ? + ?
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 142 synchronous to asynchronous odt mode transition during power-down entry if dll is selected to be frozen in precharge power-down mode by the setting of bit a12 in mr0 to 0 there is a transition period around power-down entry, where the ddr3 sdram may show either synchronous or asynchronous odt behavior. this transition period ends when cke is first registered low and starts tanpd before that. if there is a refresh command in progress while cke goes low, then the transiti on period ends trfc after the refresh command. tanpd is equal to (wl ? + + + + : ck odt command cke dram_rtt_a_sync odt_a_sync odt_b_tran dram_rtt_b_tran dram_rtt_c_async odt_c_async /ck taof (min.) taof (max.) pd entry transition period tanpd trfc odtloff ref nop nop rtt rtt odtloff + taofpd (min.) taofpd (max.) taofpd (max.) taofpd (min.) taofpd (min.) odtloff + taofpd (max.) synchronous to asynchronous transition during precharge power-down (with dll frozen) entry (al = 0; cwl = 5; tanpd = wl ? =
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 143 asynchronous to synchronous odt mode transition during power-down exit if dll is selected to be frozen in precharge power-down mode by the setting of bit a12 in mr0 to 0, there is also a transition period around power-down exit, where either sy nchronous or asynchronous response to a change in odt must be expected from the ddr3 sdram. this transition period starts tanpd before cke is first registered high, a nd ends txpdll after cke is first registered high. tanpd is equal to (wl ? + + + + : rtt rtt t1 t3 t5 t7 t9 t11 t13 t15 t17 t19 t21 t23 t25 t27 t29 t31 t33 t35 ck command cke dram_rtt_a_sync odt_a_sync odt_b_tran dram_rtt_b_tran dram_rtt_c_async odt_c_async /ck pd exit transition period tanpd txpdll taof (min.) taof (max.) odtloff taofpd (max.) taofpd (min.) odtloff + taof (max.) odtloff + taof (min.) taofpd (max.) taofpd (min.) nop nop asynchronous to synchronous transition during pr echarge power-down (with dll frozen) exit (cl = 6; al = cl - 1; cwl = 5; tanpd= wl ? =
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 144 asynchronous to synchronous odt mode during short cke high and short cke low periods if the total time in precharge power-down state or idle stat e is very short, the transition periods for power-down entry and power-down exit may overlap. in this case the resp onse of the ddr3 sdram rtt to a change in odt state at the input may be synchronous or asynchronous from the st art of the power-down entry transition period to the end of the pd exit transition perio d (even if the entry period ends later than the exit period). if the total time in idle state is ve ry short, the transition periods for power-down exit and power-down entry may overlap. in this case the respons e of the ddr3 sdram rtt to a change in odt state at the input may be synchronous or asynchronous from the start of the power-down exit transiti on period to the end of the power-down entry transition period. note that in the bottom part of figure below it is assum ed that there was no refresh command in progress when idle state was entered. ref nop nop nop nop ck command cke cke /ck tanpd trfc pd entry transition period pd exit transition period tanpd txpdll tanpd txpdll tanpd short cke high transition period short cke low transition period txpdll transition period for short cke cycles with entry and exit period overlapping (al = 0, wl = 5, tanpd = wl ? =
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 145 zq calibration zq calibration command is used to calibrate dram ron and odt values. ddr3 sdram needs longer time to calibrate ron and odt at initialization and relatively smaller time to perform periodic calibrations. zqcl command is used to perform the initial calibratio n during power-up initialization sequence. this command may be issued at any time by the controller depending on the system environment. zqcl command triggers the calibration engine inside the dram and once calibration is achieved the calibrated val ues are transferred from calibration engine to dram i/o which gets re flected as updated ron and odt values. the first zqcl command issued after reset is allowed a timing period of tzqinit to perform the full calibration and the transfer of values. all other zqcl commands except th e first zqcl command issued after reset is allowed a timing period of tzqoper. zqcs command is used to perform periodic calibrations to account for voltage and temperature variations. a shorter timing window is provided to perform the calibration and tran sfer of values as defined by timing parameter tzqcs. one zqcs command can effectively correct a minimum of 0.5% (zqcorrection) of ron and rtt impedance error within 64nck for all speed bins assuming the maximum sens itivities specified in the ?output driver voltage and temperature sensitivity? an d ?odt voltage and temperature sensitivity? tables. the a ppropriate interval between zqcs commands can be determined from these tables and other application-specific parameters. one method for calculating the interval between zqcs commands, given the te mperature (tdriftrate) and voltage (vdriftrate) drift rates that the sdram is subject to in the application, is illustrated. the interval could be defined by the following formula:

where tsens = max(drttdt, drondtm) and vsens = ma x(drttdv, drondvm) define the sdram temperature and voltage sensitivities. for example, if tsens = 1.5%/ = = = : 0.5 (1.5 1) + (0.15 15) = 0.133 128ms no other activities should be performed on the dram channel by the controller for the durat ion of tzqinit, tzqoper or tzqcs. the quiet time on the dram channel allows in accurate calibration of ron and odt. once dram calibration is achieved the dram should disabl e zq current consumption path to reduce power. all banks must be precharged and trp met before zqcl or zqcs commands are issued by the controller. zq calibration commands can also be issued in parallel to dll lock time when coming out of self-refresh. upon self- refresh exit, ddr3 sdram will not perform an i/o calibrati on without an explicit zq calibration command. the earliest possible time for zq calibration command (s hort or long) after self-refresh exit is txs. in systems that share the zq resistor between devices, the controller must not allow an y overlap of tzqoper, tzqinit or tzqcs between the devices. ck a10 address cke dq bus* 2 notes: 1. cke must be continuously registered high during the calibration procedure. 2. odt must be disabled via odt signal or mrs during calibration procedure. 3. all device connected to dq bus should be high impedance during calibration. command nop/desl nop/desl zqcs valid valid zqcl hi-z activities hi-z activities a10 = l a10 = h x x tzqinit or tzq oper tzqcs zq calibration
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 146 zq external resistor value and tolerance ddr3 sdram has a 240 ?
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 147 package drawing 78-ball fbga solder ball: lead free (sn-ag-cu) 7.50 0.10 index mark 10.60 0.10 0.10 s 0.20 s 1.20 max. 0.35 0.05 s b a index mark 0.8 9.6 1.6 6.4 unit: mm 0.20 s b 78- 0.45 0.05 0.15 m sa b eca-ts2-0306-01 0.20 s a 0.8
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 148 recommended soldering conditions please consult with our sales offices for soldering conditions of the EDJ2104EDBG, edj2108edbg. type of surface mount device EDJ2104EDBG, edj2108edbg: 78-ball fbga < lead free (sn-ag-cu) >
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 149 notes for cmos devices 1 precaution against esd for mos devices exposing the mos devices to a strong electric field can cause destruction of the gate oxide and ultimately degrade the mos devices operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it, when once it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. mos devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. mos devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor mos devices on it. 2 handling of unused input pins for cmos devices no connection for cmos devices input pins can be a cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. the unused pins must be handled in accordance with the related specifications. 3 status before initialization of mos devices power-on does not necessarily define initial status of mos devices. production process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the mos devices with reset function have not yet been initialized. hence, power-on does not guarantee output pin levels, i/o settings or contents of registers. mos devices are not initialized until the reset signal is received. reset operation must be executed immediately after power-on for mos devices having reset function. cme0107
EDJ2104EDBG, edj2108edbg data sheet e1797e41 (ver. 4.1) 150 m01e1007 no part of this document may be copied or reproduced in any form or by any means without the prior written consent of elpida memory, inc. elpida memory, inc. does not assume any liability for infringement of any intellectual property rights (including but not limited to patents, copyrights, and circuit layout licenses) of elpida memory, inc. or third parties by or arising from the use of the products or information listed in this document. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of elpida memory, inc. or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of the customer's equipment shall be done under the full responsibility of the customer. elpida memory, inc. assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. [product applications] be aware that this product is for use in typical electronic equipment for general-purpose applications. elpida memory, inc. makes every attempt to ensure that its products are of high quality and reliability. however, this product is not intended for use in the product in aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment, medical equipment for life support, or other such application in which especially high quality and reliability is demanded or where its failure or malfunction may directly threaten human life or cause risk of bodily injury. customers are instructed to contact elpida memory's sales office before using this product for such applications. [product usage] design your application so that the product is used within the ranges and conditions guaranteed by elpida memory, inc., including the maximum ratings, operating supply voltage range, heat radiation characteristics, installation conditions and other related characteristics. elpida memory, inc. bears no responsibility for failure or damage when the product is used beyond the guaranteed ranges and conditions. even within the guaranteed ranges and conditions, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating elpida memory, inc. products does not cause bodily injury, fire or other consequential damage due to the operation of the elpida memory, inc. product. [usage environment] usage in environments with special characteristics as listed below was not considered in the design. accordingly, our company assumes no responsibility for loss of a customer or a third party when used in environments with the special characteristics listed below. example: 1) usage in liquids, including water, oils, chemicals and organic solvents. 2) usage in exposure to direct sunlight or the outdoors, or in dusty places. 3) usage involving exposure to significant amounts of corrosive gas, including sea air, cl 2 , h 2 s, nh 3 , so 2 , and no x . 4) usage in environments with static electricity, or strong electromagnetic waves or radiation. 5) usage in places where dew forms. 6) usage in environments with mechanical vibration, impact, or stress. 7) usage near heating elements, igniters, or flammable items. if you export the products or technology described in this document that are controlled by the foreign exchange and foreign trade law of japan, you must follow the necessary procedures in accordance with the relevant laws and regulations of japan. also, if you export products/technology controlled by u.s. export control regulations, or another country's export control laws or regulations, you must follow the necessary procedures in accordance with such laws or regulations. if these products/technology are sold, leased, or transferred to a third party, or a third party is granted license to use these products, that third party must be made aware that they are responsible for compliance with the relevant laws and regulations. the information in this document is subject to change without notice. before using this document, confirm that this is the late st version.

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